KR100888199B1 - Method of forming metal interconnection line for semiconductor device - Google Patents

Method of forming metal interconnection line for semiconductor device Download PDF

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KR100888199B1
KR100888199B1 KR1020020042258A KR20020042258A KR100888199B1 KR 100888199 B1 KR100888199 B1 KR 100888199B1 KR 1020020042258 A KR1020020042258 A KR 1020020042258A KR 20020042258 A KR20020042258 A KR 20020042258A KR 100888199 B1 KR100888199 B1 KR 100888199B1
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film
wiring
forming
diffusion barrier
copper
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KR20040008593A (en
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표성규
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure

Abstract

본 발명은 확산방지막을 구리배선 상에만 우수한 결합력으로 선택적으로 형성하여 유효 k 값의 증가, EM 특성 악화, 및 결함발생 등을 효과적으로 방지할 수 있는 반도체 소자의 금속배선 형성방법을 제공한다.The present invention provides a method for forming a metal wiring of a semiconductor device capable of effectively forming a diffusion barrier layer on the copper wiring selectively with excellent bonding force to effectively increase the effective k value, deterioration of EM characteristics, and defects.

본 발명은상부에 배선형상의 홀이 구비된 절연막이 형성된 반도체 기판을 준비하는 단계; 상기 홀에 매립되도록 절연막 상에 구리막을 증착하는 단계; 상기 구리막을 전면식각하여 구리배선을 형성함과 동시에 기판을 평탄화하는 단계; 상기 구리배선 표면에만 선택적으로 확산방지막을 형성하는 단계를 포함하는 것을 특징으로 하고, 상기 확산방지막을 형성하는 단계는, 상기 구리배선 표면에만 선택적으로 화학적강화제를 흡착하는 단계; 상기 화학적강화제가 흡착된 구리배선 표면에만 선택적으로 금속막을 증착하는 단계; 상기 금속막을 산화 또는 질화처리하여 상기 구리배선 표면에 확산방지막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법에 의해 달성될 수 있다. The present invention provides a method of manufacturing a semiconductor substrate, the method comprising: preparing a semiconductor substrate having an insulating film having a wiring hole formed thereon; Depositing a copper film on an insulating film to be filled in the hole; Etching the entire copper film to form copper wiring and planarizing the substrate; And selectively forming a diffusion barrier on only the copper wiring surface, wherein the forming of the diffusion barrier layer comprises: selectively adsorbing a chemical strengthening agent only on the copper wiring surface; Selectively depositing a metal film only on a surface of the copper wiring on which the chemical enhancer is adsorbed; It can be achieved by a method for forming a metal wiring of a semiconductor device comprising the step of oxidizing or nitriding the metal film to form a diffusion barrier on the surface of the copper wiring.

구리, 이중 데머신, 화학적강화제, 요오드, ALD, EM, 확산방지막Copper, Double Demachine, Chemical Hardener, Iodine, ALD, EM, Diffusion Barrier

Description

반도체 소자의 금속배선 형성방법{METHOD OF FORMING METAL INTERCONNECTION LINE FOR SEMICONDUCTOR DEVICE} METHODS OF FORMING METAL INTERCONNECTION LINE FOR SEMICONDUCTOR DEVICE             

도 1은 종래의 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a metal wiring formation method of a conventional semiconductor device.

도 2는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도.2 is a cross-sectional view illustrating a metal wiring forming method of a semiconductor device according to an embodiment of the present invention.

※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing

21 : 반도체 기판 22, 24, 28 : 절연막21: semiconductor substrate 22, 24, 28: insulating film

23 : 식각정지막 25 : 배리어 금속막23 etch stop film 25 barrier metal film

26 : 구리배선 27 : 확산방지막
26: copper wiring 27: diffusion barrier

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 구리를 이용한 반도체 소자의 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device using copper.

반도체 소자의 고집적화에 따른 배선 선폭의 미세화로 인하여, 선폭구현 및 배선의 신뢰성 등의 문제가 대두되고 있으며, 이를 해결하기 위한 기술로서 배선형상의 홀을 먼저 형성한 후 홀에 금속막을 배립하는 이중 데머신(dual damascene) 공정을 이용한 배선기술이 제시되었다.Due to the miniaturization of wiring line width due to high integration of semiconductor devices, problems such as line width implementation and wiring reliability have emerged. As a technique for solving this problem, a wiring-shaped hole is first formed and then a metal film is disposed in the hole. A wiring technique using a dual damascene process has been proposed.

일반적으로, 이중 데머신 공정에서는 배선물질로서 구리(Cu)를 사용하는데, 이러한 구리배선은 알루미늄(Al) 배선에 비해 전자이동(Electro-Migration : EM) 특성이 우수할 뿐만 아니라 저항값이 낮고, 알루미늄 배선과는 달리 갭매립(gap fill) 물질이 요구되지 않는다. 또한, 지연시간이 짧아 고속동작을 구현할 수 있다.In general, in the double demachine process, copper (Cu) is used as a wiring material, and the copper wiring not only has excellent electro-migration (EM) characteristics, but also has low resistance, compared to aluminum (Al) wiring. Unlike aluminum wiring, no gap fill material is required. In addition, since the delay time is short, high-speed operation can be realized.

도 1은 이러한 구리배선을 적용한 종래의 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a metal wiring forming method of a conventional semiconductor device to which such a copper wiring is applied.

도 1을 참조하면, 트랜지스터 형성 등의 소정의 공정이 완료된 반도체 기판(11) 상에 산화막의 제 1 절연막(12), 질화막(SiN)의 식각정지막(13), 및 산화막의 제 2 절연막(14)을 순차적으로 형성한다. 여기서, 제 1 절연막(12)은 비아홀(via hole)의 깊이에 해당하는 두께로 형성하고, 제 2 절연막(14)은 배선에 해당하는 두께로 형성한다. 그 다음, 제 2 절연막(14) 상부에 포토리소그라피로 제 1 포토레지스트 패턴(미도시)을 형성하고, 제 1 포토레지스트 패턴을 식각마스크로하여 제 2 절연막(14), 식각정지막(13), 및 제 1 절연막(12)을 순차적으로 식각하여 비아홀을 형성한 후, 공지된 방법으로 제 1 포토레지스트 패턴을 제거한다.Referring to FIG. 1, a first insulating film 12 of an oxide film, an etch stop film 13 of a nitride film SiN, and a second insulating film of an oxide film are formed on a semiconductor substrate 11 on which a predetermined process such as transistor formation is completed. 14) are formed sequentially. Here, the first insulating film 12 is formed to a thickness corresponding to the depth of the via hole, and the second insulating film 14 is formed to a thickness corresponding to the wiring. Next, a first photoresist pattern (not shown) is formed on the second insulating layer 14 by photolithography, and the second insulating layer 14 and the etch stop layer 13 are formed by using the first photoresist pattern as an etching mask. And the first insulating layer 12 are sequentially etched to form via holes, and then the first photoresist pattern is removed by a known method.

그리고 나서, 제 2 절연막(14) 상부에 포토리소그라피로 제 2 포토레지스트 패턴(미도시)을 형성하고, 제 2 포토레지스트 패턴을 식각마스크로하여 식각정지막 (13)이 노출되도록 제 2 절연막(14)을 식각하여 배선형상의 홀을 형성한 후, 공지된 방법으로 제 2 포토레지스트 패턴을 제거한다. 그 후, 홀 표면 상에 배리어 금속막(15)을 형성하고, 배리어 금속막(15)이 형성된 홀에 매립되도록 기판 전면 상에 구리막을 증착한 후, 구리막과 배리어 금속막(15)을 화학기계연마(Chemical Mechanical Polishing :CMP)로 제 2 절연막(14)이 노출되도록 전면식각하여 구리배선(16)을 형성함과 동시에 기판 표면을 평탄화한다. 그 다음, 구리배선(16)이 형성된 기판에 대하여 NH3 처리를 수행한 후, SiN 또는 SiC의 확산방지(diffusion barrier)막(17)을 형성하고, 확산방지막(17) 상에 제 3 절연막(18)을 형성한다. 여기서, NH3 처리는 구리배선(16)과 확산방지막(17) 사이의 결합력을 향상시키기 위하여 수행하며, 확산방지막(17)은 구리원자가 제 3 절연막(18)으로 확산되는 것을 방지한다.Thereafter, a second photoresist pattern (not shown) is formed on the second insulating layer 14 by photolithography, and the second insulating layer 14 is exposed by using the second photoresist pattern as an etching mask. 14) is etched to form wiring-shaped holes, and then the second photoresist pattern is removed by a known method. Thereafter, a barrier metal film 15 is formed on the hole surface, and a copper film is deposited on the entire surface of the substrate so as to be embedded in the hole in which the barrier metal film 15 is formed, and then the copper film and the barrier metal film 15 are chemically formed. The surface of the substrate is planarized by etching the entire surface so that the second insulating film 14 is exposed by chemical mechanical polishing (CMP). Next, after performing NH 3 treatment on the substrate on which the copper wiring 16 is formed, a diffusion barrier film 17 of SiN or SiC is formed, and a third insulating film ( 18). Here, the NH 3 treatment is performed to improve the bonding force between the copper wiring 16 and the diffusion barrier 17, and the diffusion barrier 17 prevents the diffusion of copper atoms into the third insulating film 18.

한편, 상술한 구리배선 형성에 있어서는, 구리배선 적용에 의한 지연시간 감소 및 낮은 저항값을 확보하는 것 이외에도, k값을 낮추기 위하여 낮은 k값의 절연막을 적용한다. 그러나, 구리배선을 다층배선에 적용하는 경우 구리배선(16) 및 제 2 절연막(14) 상에 형성된 확산방지막(17)도 각 층마다 적용하게 되는데, 확산방지막(17)의 비교적 높은 k값(SiN의 k=7, SiC의 k=5)에 의해 유효 k 값의 증가가 초래되어 낮은 k값의 효과를 얻을 수 없게 된다. 또한, 구리배선(16)과 SiN 또는 SiC의 확산방지막(17) 사이의 열악한 계면 신뢰성으로 인하여 확산방지막(17)의 박리(peeling)가 일어나지 않도록 구리배선(16)의 주의 깊은 표면처리가 요구되며, 이러한 열악한 계면은 전자이동틈(EM voiding)으로 작용할 가능성이 높기 때문에 EM 특성을 악화시킨다. 또한, 구리배선(16)과 확산방지막(17) 사이의 결합 (bonding)력이 약하여 결함(defect) 발생을 야기시키므로, 결함발생을 최소화하기 위하여 확산방지막(17)의 형성전에 NH3 처리의 전처리공정을 수행하는데, 이러한 공정을 제어하는데에는 많은 어려움이 있다.
On the other hand, in forming the copper wiring described above, in addition to reducing the delay time and securing low resistance value by applying the copper wiring, an insulating film having a low k value is applied to lower the k value. However, when the copper wiring is applied to the multilayer wiring, the diffusion barrier film 17 formed on the copper wiring 16 and the second insulating film 14 is also applied to each layer, and the relatively high k value of the diffusion barrier film 17 ( The increase of the effective k value is caused by k = 7 of SiN and k = 5 of SiC, so that the effect of low k value cannot be obtained. In addition, careful surface treatment of the copper wiring 16 is required to prevent peeling of the diffusion barrier 17 due to poor interface reliability between the copper wiring 16 and the diffusion barrier 17 of SiN or SiC. These poor interfaces deteriorate EM characteristics because they are likely to act as EM voiding. In addition, since the bonding force between the copper wiring 16 and the diffusion barrier film 17 is weak, causing defects, pretreatment of the NH 3 treatment prior to the formation of the diffusion barrier film 17 to minimize the occurrence of defects. There are many difficulties in controlling the process in carrying out the process.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 확산방지막을 구리배선 상에만 우수한 결합력으로 선택적으로 형성하여 유효 k 값의 증가, EM 특성 악화, 및 결함발생 등을 효과적으로 방지함으로써 소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체 소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.
The present invention has been proposed to solve the above problems of the prior art, by selectively forming a diffusion barrier film with excellent bonding force only on the copper wiring to effectively prevent the increase of the effective k value, deterioration of EM characteristics, defects, etc. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming metal wirings of a semiconductor device, which can improve device characteristics and reliability.

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 상부에 배선형상의 홀이 구비된 절연막이 형성된 반도체 기판을 준비하는 단계; 상기 홀에 매립되도록 절연막 상에 구리막을 증착하는 단계; 상기 구리막을 전면식각하여 구리배선을 형성함과 동시에 기판을 평탄화하는 단계; 상기 구리배선 표면에만 선택적으로 확산방지막을 형성하는 단계를 포함하는 것을 특징으로 하고, 상기 확산방지막을 형성하는 단계는, 상기 구리배선 표면에만 선택적으로 화학적강화제를 흡착하는 단계; 상기 화학적강화제가 흡착된 구리배선 표면에만 선택적으로 금속막을 증착하는 단계; 상기 금속막을 산화 또는 질화처리하여 상기 구리배선 표면에 확산방지막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention comprises the steps of preparing a semiconductor substrate having an insulating film having a wiring-shaped hole thereon; Depositing a copper film on an insulating film to be filled in the hole; Etching the entire copper film to form copper wiring and planarizing the substrate; And selectively forming a diffusion barrier on only the copper wiring surface, wherein the forming of the diffusion barrier layer comprises: selectively adsorbing a chemical strengthening agent only on the copper wiring surface; Selectively depositing a metal film only on a surface of the copper wiring on which the chemical enhancer is adsorbed; It can be achieved by a method for forming a metal wiring of a semiconductor device comprising the step of oxidizing or nitriding the metal film to form a diffusion barrier on the surface of the copper wiring.

여기서, 화학적강화제로서는 CH3I, CH2I2, C2H5I 등의 요오드함유 액체화합물, 순수 요오드 개스, 요오드함유개스, 수증기, 및 주기율표 상에서 7족 원소들인 F, Cl, Br, I, At의 액체 상태 및 기체 상태 중 선택되는 하나를 이용하고, 화학적강화제의 흡착은 -20 내지 300℃의 온도에서 1초 내지 10분 동안 수행한다.Here, as the chemical enhancer, iodine-containing liquid compounds such as CH 3 I, CH 2 I 2 , C 2 H 5 I, pure iodine gas, iodine-containing gas, water vapor, and Group 7 elements F, Cl, Br, I on the periodic table , At and using at least one selected from the liquid and gaseous state, the adsorption of the chemical enhancer is carried out for 1 second to 10 minutes at a temperature of -20 to 300 ℃.

또한, 금속막은 Al막, W막 및 Ni막 중 선택되는 하나, 바람직하게 Al막으로 CVD 나 ALD 방식으로 5 내지 1000Å의 두께로 형성하며, 확산방지막은 Al2O3막, Al2O3/Al막, 또는 AlN막으로 형성한다. 또한, 금속막의 산화 또는 질화처리는 플라즈마처리나 노어닐링처리로 수행한다.In addition, the metal film is an Al film, one selected from a W film, and Ni film, preferably formed from a 5 to a thickness of 1000Å as a CVD or ALD method as Al film, a diffusion preventive film is Al 2 O 3 film, the Al 2 O 3 / It is formed of an Al film or an AlN film. In addition, the oxidation or nitriding treatment of the metal film is performed by plasma treatment or no annealing treatment.

또한, 구리배선의 형성 후 확산방지막을 형성하기 전에 세정공정을 수행하고, 확산방지막의 형성 후 기판을 DI＋산의 조합으로 세정한다.Further, after the formation of the copper wiring, the cleaning process is performed before the diffusion barrier is formed, and after the formation of the diffusion barrier, the substrate is washed with a combination of DI + acid.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도 2는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하 기 위한 단면도이다.2 is a cross-sectional view for describing a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.

도 2를 참조하면, 트랜지스터 형성 등의 소정의 공정이 완료된 반도체 기판(21) 상에 산화막의 제 1 절연막(22), 질화막(SiN)의 식각정지막(23), 및 산화막의 제 2 절연막(24)을 순차적으로 형성한다. 여기서, 제 1 절연막(22)은 비아홀의 깊이에 해당하는 두께로 형성하고, 제 2 절연막(24)은 배선에 해당하는 두께로 형성한다. 그 다음, 제 2 절연막(24) 상부에 포토리소그라피로 제 1 포토레지스트 패턴(미도시)을 형성하고, 제 1 포토레지스트 패턴을 식각마스크로하여 제 2 절연막(24), 식각정지막(23), 및 제 1 절연막(22)을 순차적으로 식각하여 비아홀을 형성한 후, 공지된 방법으로 제 1 포토레지스트 패턴을 제거한다.Referring to FIG. 2, a first insulating film 22 of an oxide film, an etch stop film 23 of a nitride film SiN, and a second insulating film of an oxide film are formed on a semiconductor substrate 21 on which a predetermined process such as transistor formation is completed. 24) are formed sequentially. Here, the first insulating film 22 is formed to a thickness corresponding to the depth of the via hole, and the second insulating film 24 is formed to a thickness corresponding to the wiring. Next, a first photoresist pattern (not shown) is formed on the second insulating layer 24 by photolithography, and the second insulating layer 24 and the etch stop layer 23 are formed by using the first photoresist pattern as an etching mask. And the first insulating layer 22 are sequentially etched to form via holes, and then the first photoresist pattern is removed by a known method.

그리고 나서, 제 2 절연막(24) 상부에 포토리소그라피로 제 2 포토레지스트 패턴(미도시)을 형성하고, 제 2 포토레지스트 패턴을 식각마스크로하여 식각정지막(23)이 노출되도록 제 2 절연막(24)을 식각하여 배선형상의 홀을 형성한 후, 공지된 방법으로 제 2 포토레지스트 패턴을 제거한다. 그 후, 홀 표면 상에 배리어 금속막(25)을 형성하고, 배리어 금속막(25)이 형성된 홀에 매립되도록 기판 전면 상에 구리막을 증착한 후, 구리막과 배리어 금속막(25)을 CMP로 제 2 절연막(14)이 노출되도록 전면식각하여 구리배선(26)을 형성함과 동시에 기판 표면을 평탄화한다.Thereafter, a second photoresist pattern (not shown) is formed on the second insulating layer 24 by photolithography, and the second insulating layer 23 is exposed to expose the etch stop layer 23 by using the second photoresist pattern as an etching mask. 24) is etched to form wiring-shaped holes, and then the second photoresist pattern is removed by a known method. Thereafter, a barrier metal film 25 is formed on the hole surface, and a copper film is deposited on the entire surface of the substrate so as to be embedded in the hole in which the barrier metal film 25 is formed, and then the copper film and the barrier metal film 25 are CMP. In order to expose the second insulating layer 14, the entire surface is etched to form the copper wiring 26 and the surface of the substrate is planarized.

그 다음, 상기 기판의 표면을 세정한 후, 구리배선(26) 표면을 화학적강화제 (Chemical Enhancer)로 표면처리를 수행하여 구리배선(26)의 표면에만 선택적으로 화학강화제를 흡착시킨다. 즉, 화학적강화제는 산화막등의 절연막(14)에서는 흡착 이 이루어지지 않기 때문에, 구리배선(26) 표면에만 선택적으로 흡착시킬 수 있으며, 이후 Al막의 증착시 촉매제로 작용한다. 바람직하게, 화학적강화제의 표면처리는 화학적강화제로서 CH3I, CH2I2, C2H5I 등의 요오드(I)함유 액체화합물, 순수 요오드 개스(pure I2), 요오드(I)함유개스, 수증기(Water vapor), 및 주기율표 상에서 7족 원소들인 F, Cl, Br, I, At의 액체 상태 및 기체 상태 중 선택되는 하나를 이용하여, -20 내지 300℃의 온도에서 1초 내지 10분 동안 수행한다. 그 후, 화학기상증착(Chemical Vapor Deposition; CVD) 또는 원자층증착(Atomic Layer Deposition; ALD) 방식으로 Al막을 증착하여 요오드가 흡착된 구리배선(26) 표면에만 선택적으로 Al막을 5 내지 1000Å의 두께로 형성한 다음, 산화 또는 질화처리를 수행하여 구리배선(26) 표면 상에만 선택적으로 Al2O3막, Al2O3/Al막, 또는 AlN막 등의 확산방지막(27)을 형성한다. 즉, 요오드는 Al막의 증착속도를 높이는 촉매역할을 하며 인큐베이션 타임(incubation time)이 거의 없어지게 되어 증착온도를 감소시켜, 요오드가 흡착된 구리배선(25) 표면에만 선택적으로 Al막의 증착이 일어나도록 한다. Then, after cleaning the surface of the substrate, the surface of the copper wiring 26 is subjected to a chemical enhancer (Chemical Enhancer) to selectively adsorb the chemical enhancer only to the surface of the copper wiring 26. That is, since the chemical enhancer is not adsorbed in the insulating film 14, such as an oxide film, it can be selectively adsorbed only on the surface of the copper wiring 26, and then acts as a catalyst during deposition of the Al film. Preferably, the surface treatment of the chemical reinforcing agent is an iodine (I) -containing liquid compound such as CH 3 I, CH 2 I 2 , C 2 H 5 I, pure iodine gas (pure I 2 ), iodine (I) containing 1 second to 10 at a temperature of -20 to 300 ° C., using one selected from gaseous, water vapor, and liquid and gaseous states of Group 7 elements F, Cl, Br, I, At on the periodic table. Run for minutes. Subsequently, an Al film is deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) to selectively deposit an Al film on the surface of the copper wiring 26 on which iodine is adsorbed. Next, an oxidation or nitriding treatment is performed to selectively form a diffusion barrier 27 such as an Al 2 O 3 film, an Al 2 O 3 / Al film, or an AlN film only on the copper wiring 26 surface. That is, iodine acts as a catalyst to increase the deposition rate of the Al film and incubation time (incubation time) is almost eliminated to reduce the deposition temperature, so that the Al film is selectively deposited only on the surface of the copper wiring 25 on which iodine is adsorbed. do.

여기서, Al막 대신 W막 이나 Ni막과 같은 금속막을 형성할 수도 있고, 산화 또는 질화처리는 플라즈마처리나 노어닐링(furnace annealing) 처리로 수행하며, 산화처리는 자연산화법으로도 수행할 수 있다. 바람직하게, 플라즈마처리는 반응처리(reaction treatment)를 이용한 리모트(remote) 플라즈마나, 단일 또는 이중 프리퀀시 에치가 가능한 플라즈마 에치(etch)로 수행한다. 또한, 플라즈마 처리는 O2, O3 개스 또는 그의 혼합개스나 H2O 개스를 사용하여, 1.0 내지 1000sccm의 개스유량과 -50 내지 400℃의 온도 및 0.1 내지 10KW의 플라즈마 전력하에서 1초 내지 10분 동안 단일스텝이나 1 내지 10회의 다단계로 수행한다. 또한, 플라즈마 처리시, 웨이퍼의 온도는 10 내지 350℃ 정도로 유지하고, 웨이퍼와 샤워헤드 사이의 간격은 2 내지 50㎚로 하며 챔버압력은 0.3 내지 10Torr로 설정한다. 그 후, DI＋산(acid) 조합의 세정공정을 수행한 후, 기판 전면 상에 제 3 절연막(28)을 형성한다.Here, a metal film such as a W film or a Ni film may be formed instead of the Al film, and the oxidation or nitriding treatment may be performed by a plasma treatment or a furnace annealing treatment, and the oxidation treatment may be performed by a natural oxidation method. Preferably, the plasma treatment is performed by remote plasma using reaction treatment, or plasma etch capable of single or double frequency etch. In addition, the plasma treatment is performed using O 2 , O 3 gas, or a mixed gas or H 2 O gas, at a flow rate of 1.0 to 1000 sccm, a temperature of -50 to 400 ° C., and a plasma power of 0.1 to 10 KW, for 1 second to 10 seconds. This may be done in a single step or in multiple stages of one to ten times for minutes. In addition, during plasma processing, the temperature of the wafer is maintained at about 10 to 350 ° C., the gap between the wafer and the showerhead is set to 2 to 50 nm, and the chamber pressure is set to 0.3 to 10 Torr. Thereafter, after performing a washing process of the DI + acid combination, a third insulating film 28 is formed on the entire surface of the substrate.

상기 실시예에 의하면, 요오드와 같은 화학적강화제를 적용하여 구리배선 (26) 표면에만 선택적으로 확산방지막(27)을 형성함에 따라 절연막의 유효 k값을 크게 감소시킬 수 있다. 또한, 요오드의 흡착에 의해 확산방지막(27)을 형성하기 때문에, 확산방지막(27)과 구리배선(26) 사이의 계면신뢰성 및 결합력이 향상되어 EM 특성을 강화시킬 수 있을 뿐만 아니라, NH3 처리 등의 전처리 공정 및 확산방지막의 직접적인 증착공정이 배제되므로 결함발생 제어가 용이해진다.According to the above embodiment, by applying a chemical strengthening agent such as iodine to selectively form the diffusion barrier 27 only on the surface of the copper wiring 26, the effective k value of the insulating film can be greatly reduced. In addition, since the diffusion barrier 27 is formed by adsorption of iodine, the interfacial reliability and bonding strength between the diffusion barrier 27 and the copper wiring 26 can be improved, thereby enhancing the EM characteristics and NH 3 treatment. Since the pretreatment process and the direct deposition process of the diffusion barrier film are excluded, defect control is facilitated.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 확산방지막을 요오드 등의 화학강화제를 이용하여 우수한 결합력을 갖도록 구리배선 상에만 선택적으로 형성함에 따라, 유효 k 값의 증가, EM 특성 악화, 및 결함발생 등의 문제를 해결함으로써, 소자의 소자의 특성 및 신뢰성을 향상시킬 수 있다.
According to the present invention, the diffusion barrier layer is selectively formed only on the copper wiring to have excellent bonding strength by using a chemical strengthening agent such as iodine, thereby solving problems such as an increase in the effective k value, deterioration of EM characteristics, and defects. The characteristics and reliability of the device of the device can be improved.

Claims (11)

상부에 배선형상의 홀이 구비된 절연막이 형성된 반도체 기판을 준비하는 단계;Preparing a semiconductor substrate having an insulating film having a wiring hole formed thereon; 상기 홀에 매립되도록 절연막 상에 구리막을 증착하는 단계;Depositing a copper film on an insulating film to be filled in the hole; 상기 구리막을 전면식각하여 구리배선을 형성함과 동시에 기판을 평탄화하는 단계; 및 Etching the entire copper film to form copper wiring and planarizing the substrate; And 상기 구리배선 표면에만 선택적으로 확산방지막을 형성하는 단계를 포함하는 것을 특징으로 하고, 상기 확산방지막을 형성하는 단계는,And selectively forming a diffusion barrier layer on only the copper wiring surface, wherein the forming of the diffusion barrier layer comprises: 상기 구리배선 표면에만 선택적으로 화학적강화제를 흡착하는 단계;Selectively adsorbing a chemical enhancer only on the copper wiring surface; 상기 화학적강화제가 흡착된 구리배선 표면에만 선택적으로 금속막을 증착하는 단계; 및 Selectively depositing a metal film only on a surface of the copper wiring on which the chemical enhancer is adsorbed; And 상기 금속막을 산화 또는 질화처리하여 상기 구리배선 표면에 확산방지막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And forming a diffusion barrier on the surface of the copper wiring by oxidizing or nitriding the metal film. 삭제delete 제 1 항에 있어서, The method of claim 1, 상기 화학적강화제로서 CH3I, CH2I2, C2H5I 등의 요오드함유 액체화합물, 순수 요오드 개스, 요오드함유개스, 수증기, 및 주기율표 상에서 7족 원소들인 F, Cl, Br, I, At의 액체 상태 및 기체 상태 중 선택되는 하나를 이용하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.As the chemical enhancer, iodine-containing liquid compounds such as CH 3 I, CH 2 I 2 , C 2 H 5 I, pure iodine gas, iodine-containing gas, water vapor, and Group 7 elements on the periodic table, F, Cl, Br, I, A method for forming metal wiring in a semiconductor device, comprising using at least one selected from a liquid state and a gas state. 제 1 항 또는 제 3 항에 있어서, The method according to claim 1 or 3, 상기 화학적강화제의 흡착은 -20 내지 300℃의 온도에서 1초 내지 10분 동안 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Adsorption of the chemical strengthening agent is a metal wiring forming method of the semiconductor device, characterized in that performed for 1 second to 10 minutes at a temperature of -20 to 300 ℃. 제 1 항에 있어서, The method of claim 1, 상기 금속막은 Al막, W막 및 Ni막 중 선택되는 하나로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And the metal film is formed of one selected from an Al film, a W film, and a Ni film. 제 1 항 또는 제 5 항에 있어서, The method according to claim 1 or 5, 상기 금속막은 CVD 나 ALD 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The metal film is a metal wiring forming method of a semiconductor device, characterized in that formed by CVD or ALD method. 제 6 항에 있어서, The method of claim 6, 상기 금속막은 5 내지 1000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The metal film forming method of the semiconductor device, characterized in that formed in a thickness of 5 to 1000Å. 제 1 항 또는 제 5 항에 있어서, The method according to claim 1 or 5, 상기 확산방지막은 Al2O3막, Al2O3/Al막, 또는 AlN막인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The diffusion barrier layer is an Al 2 O 3 film, Al 2 O 3 / Al film, or a metal wiring forming method of a semiconductor device, characterized in that the AlN film. 제 1 항에 있어서, The method of claim 1, 상기 산화 또는 질화처리는 플라즈마처리나 노어닐링처리로 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Wherein the oxidation or nitriding treatment is performed by plasma treatment or no annealing treatment. 제 1 항에 있어서, The method of claim 1, 상기 구리배선의 형성 후 확산방지막을 형성하기 전에 세정공정을 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And forming a diffusion barrier after forming the copper wiring, and performing a cleaning process. 제 1 항에 있어서, The method of claim 1, 상기 확산방지막이 형성된 기판을 DI＋산의 조합으로 세정하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And cleaning the substrate on which the diffusion barrier film is formed by a combination of DI + acid.
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