KR100587600B1 - Method for forming metal wiring using dual damascene process - Google Patents

Method for forming metal wiring using dual damascene process Download PDF

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KR100587600B1
KR100587600B1 KR1020020078368A KR20020078368A KR100587600B1 KR 100587600 B1 KR100587600 B1 KR 100587600B1 KR 1020020078368 A KR1020020078368 A KR 1020020078368A KR 20020078368 A KR20020078368 A KR 20020078368A KR 100587600 B1 KR100587600 B1 KR 100587600B1
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oxide film
film
metal wiring
forming
nitride film
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KR20040050516A (en
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최일상
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 듀얼 다마신 공정을 이용한 금속배선 형성방법을 개시한다. 개시된 본 발명의 방법은, 하부 금속배선이 형성된 반도체 기판 상에 비아홀용 제1산화막과 식각정지막용 질화막 및 배선용 제2산화막을 차례로 증착하는 단계와, 상기 제2산화막과 질화막 및 제1산화막을 식각하여 하부 금속배선을 노출시키는 비아홀을 형성하는 단계와, 상기 질화막을 식각정지막으로해서 비아홀 상측의 제2산화막 부분을 식각하여 트렌치를 형성하는 단계와, 상기 콘택홀 및 트렌치 내에 금속막을 매립시켜 상부 금속배선을 형성하는 단계를 포함하는 듀얼 다마신 공정을 이용한 금속배선 형성방법에 있어서, 상기 질화막은 상기 제1산화막 증착 후에 반응 가스로서 질소 가스를 추가 주입하여 증착하고, 상기 제3산화막은 질소 가스의 주입을 해제하여 증착하며, 상기 제1산화막과 질화막 및 제3산화막의 증착은 인-시튜(In-situ) 방식으로 수행하는 것을 특징으로 한다. 본 발명에 따르면, 제1산화막과 질화막 및 제2산화막의 형성을 단일 챔버 내에서 인-시튜 방식으로 진행할 수 있으므로, 공정 단순화를 통해 생산성을 향상시킬 수 있다. The present invention discloses a metallization method using a dual damascene process. The disclosed method includes sequentially depositing a via oxide first oxide film, an etch stop film nitride film and a second wiring oxide film on a semiconductor substrate on which a lower metal wiring is formed, and etching the second oxide film, the nitride film, and the first oxide film. Forming a via hole exposing the lower metal wiring; forming a trench by etching a portion of the second oxide layer on the upper side of the via hole using the nitride film as an etch stop layer; and filling a metal film in the contact hole and the trench In the metal wiring forming method using a dual damascene process comprising the step of forming a metal wiring, the nitride film is deposited by additional injection of nitrogen gas as a reaction gas after the deposition of the first oxide film, the third oxide film is nitrogen gas Deposition of the first oxide film, the nitride film, and the third oxide film are carried out by depositing the deposited oxide, and the deposition is performed in an in-situ manner. It is characterized by performing as. According to the present invention, since the formation of the first oxide film, the nitride film, and the second oxide film can be performed in-situ within a single chamber, productivity can be improved by simplifying the process.

Description

듀얼 다마신 공정을 이용한 금속배선 형성방법{Method for forming metal wiring using dual damascene process}Method for forming metal wiring using dual damascene process

도 1a 내지 도 1d는 본 발명의 실시예에 따른 듀얼 다마신 공정을 이용한 금속배선 형성방법을 설명하기 위한 공정별 단면도. 1A to 1D are cross-sectional views of processes for explaining a method of forming metal wirings using a dual damascene process according to an exemplary embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1 : 반도체 기판 2 : 하부 금속배선1 semiconductor substrate 2 lower metal wiring

3 : 층간절연막 4 : 캡핑질화막3: interlayer insulating film 4: capping nitride film

5 : 비아산화막 6 : 질화막5: non-oxide film 6: nitride film

7 : 배선산화막 8 : 상부 금속배선7: wiring oxide film 8: upper metal wiring

V : 비아홀 T : 트렌치V: Via Hole T: Trench

본 발명은 듀얼 다마신(Dual damascene) 공정을 이용한 금속배선 형성방법에 관한 것으로, 보다 상세하게는, 공정 단순화를 통해 생산성을 향상시키기 위한 방법에 관한 것이다.The present invention relates to a method for forming metal wiring using a dual damascene process, and more particularly, to a method for improving productivity through process simplification.

반도체 메모리 소자의 집적도가 증가함에 따라, 메모리 셀들은 스택(Stack) 구조화되고 있으며, 이에 따라, 각 셀들간의 전기적 연결을 위한 금속배선도 배선 설계를 용이하게 할 수 있는 다층 구조로 형성되고 있다. 이러한 다층금속배선 구조는 배선 설계가 자유롭고, 배선저항 및 전류용량 등의 설정을 여유있게 할 수 있다는 잇점이 있다. As the degree of integration of semiconductor memory devices increases, memory cells are stacked in structure, and thus, metal wiring diagrams for electrical connection between the cells are formed in a multi-layer structure that can facilitate wiring design. Such a multilayer metal wiring structure has advantages in that the wiring design can be freely set and the setting of the wiring resistance and the current capacity can be made free.

한편, 금속배선 물질로서는 전기 전도도가 비교적 우수한 알루미늄(Al) 또는 그의 합금막이 주로 사용되어 왔으며, 최근에는 텅스텐은 물론, 알루미늄에 비해 전기 전도도가 더 우수한 구리(Cu)를 이용하려는 연구가 진행되고 있다.Meanwhile, aluminum (Al) or an alloy film thereof having relatively high electrical conductivity has been mainly used as a metal wiring material, and recently, studies have been conducted to use tungsten as well as copper (Cu) having better electrical conductivity than aluminum. .

그러나, 종래 기술에 따라 금속배선을 형성할 경우에는 금속막의 식각 특성과 관련하여 금속막의 건식 식각 후에 인접하는 금속배선들간에 브릿지(bridge)가 발생할 수 있고, 금속막이 화합물 형태로 잔류됨으로써 소자의 전기적 특성에 악영향을 미치는 문제점이 있다. 특히, 이러한 문제는 반도체 소자의 고집적화가 진행됨에 따라, 더욱 심각할 것으로 예상된다. However, in the case of forming the metal wiring according to the prior art, a bridge may occur between adjacent metal wirings after dry etching of the metal film in relation to the etching characteristics of the metal film, and the metal film remains in the form of a compound, thereby causing electrical There is a problem that adversely affects the characteristics. In particular, this problem is expected to be more serious as the integration of semiconductor devices proceeds.

따라서, 최근에는 상기와 같은 문제점들을 해결하기 위하여 듀얼 다마신 공정을 이용한 금속배선 형성방법이 제안되었다.Therefore, recently, in order to solve the above problems, a method of forming a metal wiring using a dual damascene process has been proposed.

이하에서는 기제안된 종래의 듀얼 다마신 공정을 이용한 금속배선 형성방법을 간략하게 설명하도록 한다. Hereinafter, a method of forming a metal wiring by using the conventional dual damascene process, which has been previously described, will be described briefly.

먼저, 하부 금속배선이 형성된 반도체 기판 상에 층간절연막을 형성하고, 그 표면을 평탄화시킨다. 그런다음, 평탄화된 층간절연막 상에 캡핑질화막(capping nitride)을 증착한다. First, an interlayer insulating film is formed on a semiconductor substrate on which lower metal wiring is formed, and the surface thereof is planarized. Then, a capping nitride is deposited on the planarized interlayer insulating film.

이어서, 캡핑질화막 상에 비아홀용 산화막(이하, "비아산화막"이라 칭함)과 식각정지막용 질화막 및 배선용 산화막(이하, "배선산화막"이라 칭함)을 차례로 증착한다. Next, a via hole oxide film (hereinafter referred to as a "via oxide film"), an etching stop film nitride film and a wiring oxide film (hereinafter referred to as a "wiring oxide film") are deposited on the capping nitride film.

다음으로, 상기 배선산화막과 질화막 및 비아산화막을 식각하여 하부 금속배선을 노출시키는 비아홀을 형성하고, 그런다음, 상기 비아홀 상측의 배선산화막을 식각하여 트렌치를 형성한다. 이때, 상기 트렌치를 형성하기 위한 배선산화막의 식각은 질화막을 식각정지막으로 이용하여 수행한다.Next, the wiring oxide film, the nitride film, and the via oxide film are etched to form a via hole exposing the lower metal wiring, and then the wiring oxide film on the upper side of the via hole is etched to form a trench. In this case, the etching of the wiring oxide film for forming the trench is performed by using the nitride film as an etch stop film.

그리고나서, 상기 비아홀을 포함한 트렌치를 매립하도록 배선산화막 상에 금속막, 예컨데, 구리막을 증착한 상태에서, 상기 배선산화막이 노출될 때까지 상기 구리막을 CMP(Chemical Mechanical Polishing)하여 하부 금속배선과 콘택되는 상부 금속배선을 형성한다. Then, in a state in which a metal film, for example, a copper film is deposited on the wiring oxide film to fill the trench including the via hole, the copper film is chemically polished (CMP) until the wiring oxide film is exposed, thereby contacting the lower metal wiring. The upper metal wiring is formed.

그러나, 전술한 바와 같은 종래의 듀얼 다마신 공정을 이용한 금속배선 형성방법에 따르면, 비아산화막과 질화막 및 배선산화막은, 일단, 임의의 챔버에서 상기 비아산화막을 증착한 후, 다른 챔버로 옮겨 산화막과의 식각선택비를 갖는 Si3N4, SiCN 또는 SiC 등의 질화막을 증착하고, 그리고나서, 다시 원래 산화막 챔버로 옮겨 배선산화막을 증착해야 하므로, 공정이 복잡함은 물론 장비 및 비용 상의 문제가 있다. However, according to the method of forming a metal wiring using the conventional dual damascene process as described above, the via oxide film, the nitride film, and the wiring oxide film, once the via oxide film is deposited in an arbitrary chamber, are transferred to another chamber, and the oxide film and the like. Since a nitride film such as Si 3 N 4 , SiCN, or SiC having an etch selectivity of E, is deposited, and then transferred back to the original oxide chamber to deposit a wiring oxide, there is a complicated process and a problem in equipment and cost.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 비아산화막, 질화막 및 배선산화막의 형성 공정을 단순화시켜 생산성을 향상시킬 수 있는 듀얼 다마신 공정을 이용한 금속배선 형성방법을 제공함에 그 목적이 있다. Accordingly, the present invention has been made to solve the above problems, to provide a method for forming a metal wiring using a dual damascene process that can improve the productivity by simplifying the formation process of the via oxide film, nitride film and wiring oxide film. There is a purpose.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 하부 금속배선이 형성된 반도체 기판 상에 비아홀용 제1산화막과 식각정지막용 질화막 및 배선용 제2산화막을 차례로 증착하는 단계와, 상기 제2산화막과 질화막 및 제1산화막을 식각하여 하부 금속배선을 노출시키는 비아홀을 형성하는 단계와, 상기 질화막을 식각정지막으로해서 비아홀 상측의 제2산화막 부분을 식각하여 트렌치를 형성하는 단계와, 상기 콘택홀 및 트렌치 내에 금속막을 매립시켜 상부 금속배선을 형성하는 단계를 포함하는 듀얼 다마신 공정을 이용한 금속배선 형성방법에 있어서, 상기 질화막은 상기 제1산화막 증착 후에 반응 가스로서 N2, NO, N2O 및 NH3로 구성된 그룹으로부터 선택되는 어느 하나를 추가 주입하여 증착하고, 상기 제3산화막은 질소 가스의 주입을 해제하여 증착하며, 상기 제1산화막과 질화막 및 제3산화막의 증착은 인-시튜(In-situ) 방식으로 수행하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 금속배선 형성방법을 제공한다. In order to achieve the above object, the present invention, the step of depositing the first oxide film for the via hole, the nitride film for the etch stop film and the second oxide film for wiring on the semiconductor substrate on which the lower metal wiring is formed, the second oxide film and the nitride film And forming a via hole through which the first oxide film is etched to expose the lower metal wiring, and forming a trench by etching the second oxide layer on the upper side of the via hole by using the nitride film as an etch stop layer, and forming the trench. A method of forming a metal wiring using a dual damascene process, including forming a top metal wiring by embedding a metal film in the inside, wherein the nitride film is N 2 , NO, N 2 O, and NH as a reaction gas after deposition of the first oxide film. Any one selected from the group consisting of 3 is further injected and deposited, and the third oxide film is deposited by releasing the injection of nitrogen gas. In addition, the deposition of the first oxide film, the nitride film and the third oxide film provides a method for forming metal wiring using a dual damascene process, which is performed in an in-situ method.

삭제delete

상기 제1 및 제2산화막은 챔버 내에 TEOS 가스를 50∼300㏄의 유량, 그리고, O2 가스를 50∼1000㏄의 유량으로 주입하면서 온도를 300∼400℃, 그리고, 압력을 0.01∼300Torr로 하는 조건하에서 PECVD 방식에 따라 각각 3000∼4000Å 및 4000∼ 5000Å의 두께로 증착한다. The first and second oxide films have a temperature of 300 to 400 ° C. and a pressure of 0.01 to 300 Torr while injecting TEOS gas into the chamber at a flow rate of 50 to 300 kPa, and O 2 gas at a flow rate of 50 to 1000 kPa. Under the condition of the above deposition, the films were deposited to a thickness of 3000 to 4000 mmW and 4000 to 5000 mmW, respectively, according to the PECVD method.

상기 질화막은 챔버내에 TEOS 가스를 50∼300㏄의 유량, O2 가스를 50∼1000㏄의 유량, NH3 가스를 300∼3000㏄의 유량으로 주입하면서, 온도를 300∼400℃, 압력을 0.01∼300Torr로 하는 조건하에서 PECVD 방식에 따라 500∼1000Å의 두께로 증착한다. The nitride film has a temperature of 300 to 400 DEG C and a pressure of 0.01 while injecting TEOS gas at a flow rate of 50 to 300 kPa, O 2 gas at a flow rate of 50 to 1000 kPa, and NH 3 gas at a flow rate of 300 to 3000 kPa. The deposition was carried out at a thickness of 500 to 1000 mW by the PECVD method under the condition of -300 Torr.

또한, 본 발명은, 하부 금속배선이 형성된 반도체 기판 상에 비아홀용 제1산화막과 식각정지막용 질화막 및 배선용 제2산화막을 차례로 형성하는 단계와, 상기 제2산화막과 질화막 및 제1산화막을 식각하여 하부 금속배선을 노출시키는 비아홀을 형성하는 단계와, 상기 질화막을 식각정지막으로해서 비아홀 상측의 제2산화막 부분을 식각하여 트렌치를 형성하는 단계와, 상기 콘택홀 및 트렌치 내에 금속막을 매립시켜 상부 금속배선을 형성하는 단계를 포함하는 듀얼 다마신 공정을 이용한 금속배선 형성방법에 있어서, 상기 질화막은 상기 제1산화막 증착 후에 그 표면을 플라즈마 처리하는 것을 통해 질화(nitridation)시켜 형성하고, 상기 제2산화막은 질화되어 형성된 질화막 상에 증착하며, 상기 제1산화막과 질화막 및 제3산화막은 인-시튜(In-situ) 방식으로 형성하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 금속배선 형성방법을 제공한다. In addition, the present invention comprises the steps of sequentially forming the first oxide film for the via hole, the nitride film for the etch stop film and the second oxide film for the wiring on the semiconductor substrate on which the lower metal wiring is formed, by etching the second oxide film, the nitride film and the first oxide film Forming a via hole exposing the lower metal wiring; forming a trench by etching the second oxide film portion over the via hole using the nitride film as an etch stop layer; and filling a metal film in the contact hole and the trench In the method of forming a metal wiring using a dual damascene process comprising the step of forming a wiring, the nitride film is formed by nitriding through the plasma treatment of the surface after the deposition of the first oxide film, the second oxide film Is deposited on the nitride film formed by nitriding, and the first oxide film, the nitride film, and the third oxide film are in-situ. It provides a dual damascene metal interconnection forming method using a process comprising a step of forming a.

여기서, 상기 플라즈마 처리는 NH3 또는 N2O 가스의 유량을 300∼3000㏄로 하면서 파워를 50∼1000W로 하여 10∼120초 동안 수행한다. The plasma treatment is performed for 10 to 120 seconds with the power of 50 to 1000 W while the flow rate of NH 3 or N 2 O gas is 300 to 3000 kPa.

상기 제1 및 제2산화막은 챔버 내에 TEOS 가스를 50∼300㏄의 유량, O2 가스를 50∼1000㏄의 유량으로 주입하면서 온도를 300∼400℃, 압력을 0.01∼300Torr로 하는 조건하에서 PECVD 방식에 따라 각각 3000∼4000Å 및 4000∼5000Å의 두께로 증착한다. The first and second oxide films were PECVD under conditions of 300 to 400 ° C. and a pressure of 0.01 to 300 Torr while injecting TEOS gas at a flow rate of 50 to 300 kPa and O 2 gas at a flow rate of 50 to 1000 kPa. Depending on the method, it is deposited with a thickness of 3000 to 4000 mmW and 4000 to 5000 mmW, respectively.

본 발명에 따르면, 제1산화막과 질화막 및 제2산화막의 형성을 단일 챔버 내에서 인-시튜 방식으로 진행할 수 있으므로, 공정 단순화를 통해 생산성을 향상시킬 수 있다. According to the present invention, since the formation of the first oxide film, the nitride film, and the second oxide film can be performed in-situ within a single chamber, productivity can be improved by simplifying the process.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d는 본 발명의 실시예에 따른 듀얼 다마신 공정을 이용한 금속배선 형성방법을 설명하기 위한 공정별 단면도이다. 1A to 1D are cross-sectional views illustrating processes for forming a metal wiring using a dual damascene process according to an exemplary embodiment of the present invention.

도 1a를 참조하면, 공지의 공정에 따라 하부 금속배선(2)이 형성된 반도체 기판(1) 상에 상기 하부 금속배선(2)을 덮도록 층간절연막(3)을 증착하고, 그 표면을 평탄화시킨다. 그런다음, 평탄화된 층간절연막(3) 상에 캡핑질화막(4)을 증착한다. 여기서, 상기 캡핑질화막(4)은 후속 비아홀 형성시 하부 금속배선이 손상되는 것을 방지하기 위해 형성해 준 것이다. Referring to FIG. 1A, an interlayer insulating film 3 is deposited on the semiconductor substrate 1 on which the lower metal wirings 2 are formed according to a known process to cover the lower metal wirings 2, and the surface thereof is planarized. . Then, a capping nitride film 4 is deposited on the planarized interlayer insulating film 3. Here, the capping nitride film 4 is formed to prevent the lower metal wiring from being damaged during the subsequent via hole formation.

도 1b를 참조하면, 상기 캡핑질화막(4) 상에 비아산화막(5)과 식각정지막용 질화막(6) 및 배선산화막(7)을 차례로 형성한다. 여기서, 상기 비아산화막(5)과 질화막(6) 및 배선산화막(7)의 형성은 익스-시튜(Ex-situ)로 진행하는 종래의 그것과는 달리 인-시튜(In-situ) 방식으로 진행한다. Referring to FIG. 1B, a via oxide film 5, an etch stop film nitride film 6, and a wiring oxide film 7 are sequentially formed on the capping nitride film 4. Here, the formation of the via oxide film 5, the nitride film 6, and the wiring oxide film 7 proceeds in an in-situ manner, unlike the conventional one, which proceeds by ex-situ. do.

즉, 본 발명은 비아산화막(5)과 질화막(6) 및 배선산화막(7)을 별도의 챔버 내에서 각각 증착하는 것이 아니라, 단일 챔버내에서 비아산화막(5)을 증착한 후에 질소 가스를 추가 주입하여 질화막(6)을 증착하며, 이후, 질소 가스를 해제시킨 상태로 비아산화막 형성시의 소오스 및 반응 가스만을 주입하여 배선산화막(7)을 증착한다. That is, the present invention does not deposit the via oxide film 5, the nitride film 6, and the wiring oxide film 7 in separate chambers, but rather adds nitrogen gas after depositing the via oxide film 5 in a single chamber. The nitride oxide film 6 is deposited to deposit the nitride film 6, and then the wiring oxide film 7 is deposited by injecting only a source and a reaction gas when the via oxide film is formed with nitrogen gas released.

자세하게, 상기 비아산화막(5)은 300∼400℃의 온도 및 0.01∼300Torr의 압력으로 유지된 챔버 내에 TEOS 가스를 50∼300㏄, 그리고, O2 가스를 50∼1000㏄의 유량으로 주입하는 PECVD 방식에 따라 3000∼4000Å의 두께로 증착한다. Specifically, the via oxide film 5 is a PECVD which injects TEOS gas at 50 to 300 kPa and O 2 gas at a flow rate of 50 to 1000 kPa in a chamber maintained at a temperature of 300 to 400 ° C and a pressure of 0.01 to 300 Torr. It deposits in thickness of 3000-4000 micrometers according to a system.

그런다음, 상기 온도 및 압력을 그대로 유지한 채 상기 가스들을 주입하면서 N2, NO, N2O 또는 NH3 가스중 어느 하나의 질소 가스, 바람직하게 NH3 가스를 300∼3000㏄의 유량으로 추가 주입하여 상기 비아산화막(5) 상에 500∼1000Å의 두께로 질화막(6)을 증착한다. Then, while injecting the gases while maintaining the temperature and pressure, the nitrogen gas of any one of N 2 , NO, N 2 O or NH 3 gas, preferably NH 3 gas, is added at a flow rate of 300 to 3000 Pa. The nitride film 6 is deposited on the via oxide film 5 to a thickness of 500 to 1000 mW.

그리고나서, NH3 가스의 주입을 해제한 상태로 비아산화막(5)의 증착시와 동일 온도 및 압력 조건하에서 TEOS 및 O2 가스만을 각각 50∼300㏄ 및 50∼1000㏄의 유량으로 주입하여 4000∼5000Å의 두께로 배선산화막(7)을 증착한다. Then, only the TEOS and O 2 gas were injected at a flow rate of 50 to 300 kPa and 50 to 1000 kPa, respectively, under the same temperature and pressure conditions as the deposition of the via oxide film 5 while the injection of NH 3 gas was released. The wiring oxide film 7 is deposited to a thickness of ˜5000 Pa.

이와 같이 하면, 상기 비아산화막(5)과 질화막(6) 및 배선산화막(7)을 단일 챔버 내에서 연속해서 증착할 수 있으므로, 종래의 그것과 비교해서, 공정 단순화를 얻을 수 있고, 또한, 증착 챔버가 1개만 있으면 되므로 장비 사용에 기인하는 문제도 해결될 수 있다. In this way, since the via oxide film 5, the nitride film 6 and the wiring oxide film 7 can be deposited continuously in a single chamber, the process simplification can be obtained and the deposition can be achieved in comparison with the conventional one. Since only one chamber is required, problems caused by the use of equipment can also be solved.

한편, 상기 질화막(6)은 비아산화막(5)을 증착한 후에 질소 가스의 추가 주 입하는 방식으로 증착하였지만, 상기 비아산화막(5) 표면을 질화(nitridation)시키는 것을 통해서도 형성 가능하다.On the other hand, the nitride film 6 is deposited by additionally injecting nitrogen gas after the via oxide film 5 is deposited, but may be formed by nitriding the surface of the via oxide film 5.

즉, PECVD 방식에 따라 소망하는 두께로 비아산화막(5)을 증착한 상태에서, NH3 또는 N2O 가스의 유량을 300∼3000㏄로 하면서 파워를 50∼1000W로 하는 조건으로 10∼120초 동안 상기 비아산화막(5)의 표면을 플라즈마 처리하고, 이를 통해, 상기 비아산화막(5)의 표면을 질화시켜 상기 질화막(6)을 형성할 수도 있다. That is, in the state where the via oxide film 5 was deposited by the PECVD method at a desired thickness, the flow rate of NH 3 or N 2 O gas was 300 to 3000 Pa, and the power was 10 to 120 seconds under the condition of 50 to 1000 W. The surface of the via oxide film 5 may be plasma treated, and through this, the surface of the via oxide film 5 may be nitrided to form the nitride film 6.

도 1c를 참조하면, 배선산화막(7)과 질화막(6) 및 비아산화막(5)을 식각하고, 연이어, 캡핑질화막(4)을 식각하여 하부 금속배선(2)을 노출시키는 비아홀(V)을 형성한다. 그런다음, 비아홀(V) 상측의 배선산화막 부분을 추가 식각하여 상부 금속배선 형성 영역을 한정하는 트렌치(T)를 형성한다. Referring to FIG. 1C, a via hole V for etching the wiring oxide film 7, the nitride film 6, and the via oxide film 5 is subsequently etched, and the capping nitride film 4 is etched to expose the lower metal wiring 2. Form. Then, the portion of the wiring oxide layer on the upper side of the via hole V is further etched to form the trench T defining the upper metal wiring forming region.

도 1d를 참조하면, 비아홀(V) 및 트렌치(T)를 완전 매립하도록 기판 결과물 상에 금속막, 예컨데, 구리막을 증착한다. 그런다음, 배선산화막(7)이 노출될 때까지 상기 구리막을 CMP하고, 이를 통해, 상기 하부 금속배선(2)과 콘택되는 상부 금속배선(8)을 형성하고, 이 결과로서, 다층 금속배선 구조를 형성한다. Referring to FIG. 1D, a metal film, for example, a copper film is deposited on the substrate resultant to completely fill the via hole V and the trench T. Referring to FIG. Then, the copper film is CMP until the wiring oxide film 7 is exposed, thereby forming the upper metal wiring 8 in contact with the lower metal wiring 2, as a result of which, the multi-layered metal wiring structure To form.

여기서, 상기 상부 금속배선(8)은, 도시하지는 않았으나, 베리어막을 포함하는 것으로 이해될 수 있다. Here, the upper metal wiring 8, although not shown, may be understood to include a barrier film.

이상에서와 같이, 본 발명은 비아산화막과 식각정지막용 질화막 배선산화막을 단일 챔버 내에서 인-시튜 방식으로 연속해서 증착하므로, 3단계의 공정을 1단 계로 줄일 수 있어 공정 단순화를 얻을 수 있고, 또한, 본 발명은 단일 챔버 내에서 상기한 막들을 연속해서 증착하므로 사용 장비도 줄일 수 있으며, 그래서, 생산성을 향상시킬 수 있다. As described above, since the present invention continuously deposits the via oxide film and the nitride oxide film oxide film for the etch stop film in an in-situ method in a single chamber, the process of the three steps can be reduced to one step, so that the process can be simplified. In addition, the present invention can reduce the equipment used by continuously depositing the above-mentioned films in a single chamber, so that the productivity can be improved.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (7)

하부 금속배선이 형성된 반도체 기판 상에 비아홀용 제1산화막과 식각정지막용 질화막 및 배선용 제2산화막을 차례로 증착하는 단계와, 상기 제2산화막과 질화막 및 제1산화막을 식각하여 하부 금속배선을 노출시키는 비아홀을 형성하는 단계와, 상기 질화막을 식각정지막으로해서 비아홀 상측의 제2산화막 부분을 식각하여 트렌치를 형성하는 단계와, 상기 콘택홀 및 트렌치 내에 금속막을 매립시켜 상부 금속배선을 형성하는 단계를 포함하는 듀얼 다마신 공정을 이용한 금속배선 형성방법에 있어서, Sequentially depositing a via hole first oxide film, an etch stop film nitride film, and a second oxide film for wiring on the semiconductor substrate on which the lower metal wiring is formed, and etching the second oxide film, the nitride film, and the first oxide film to expose the lower metal wiring. Forming a via hole, etching the second oxide film portion over the via hole by using the nitride film as an etch stop layer, and forming a trench in the contact hole and the trench to form an upper metal wiring; In the metal wiring forming method using a dual damascene process comprising, 상기 질화막은 상기 제1산화막 증착 후에 반응 가스로서 N2, NO, N2O 및 NH3로 구성된 그룹으로부터 선택되는 어느 하나를 추가 주입하여 증착하고, 상기 제3산화막은 질소 가스의 주입을 해제하여 증착하며, 상기 제1산화막과 질화막 및 제3산화막의 증착은 인-시튜(In-situ) 방식으로 수행하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 금속배선 형성방법. The nitride layer is deposited by additionally injecting any one selected from the group consisting of N 2 , NO, N 2 O, and NH 3 as a reaction gas after the deposition of the first oxide layer, and the third oxide layer releases the injection of nitrogen gas. And depositing the first oxide film, the nitride film, and the third oxide film by an in-situ method. 삭제delete 제 1 항에 있어서, 상기 제1 및 제2산화막은 The method of claim 1, wherein the first and second oxide film 챔버 내에 TEOS 가스를 50∼300㏄의 유량, 그리고, O2 가스를 50∼1000㏄의 유량으로 주입하면서, 온도를 300∼400℃, 압력을 0.01∼300Torr로 하는 조건하에서 PECVD 방식에 따라 각각 3000∼4000Å 및 4000∼5000Å의 두께로 증착하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 금속배선 형성방법. While injecting TEOS gas into the chamber at a flow rate of 50 to 300 kPa and O 2 gas at a flow rate of 50 to 1000 kPa, the respective temperatures were 3000 in accordance with the PECVD method under the conditions of 300 to 400 ° C and a pressure of 0.01 to 300 Torr. A metal wiring forming method using a dual damascene process, characterized in that the deposition to a thickness of -4000 kHz and 4000-5000 Å. 제 1 항에 있어서, 상기 질화막은 The method of claim 1, wherein the nitride film 챔버 내에 TEOS 가스를 50∼300㏄의 유량, O2 가스를 50∼1000㏄의 유량, 그리고, NH3 가스를 300∼3000㏄의 유량으로 주입하면서, 온도를 300∼400℃, 압력을 0.01∼300Torr로 하는 조건하에서 PECVD 방식에 따라 500∼1000Å의 두께로 증착하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 금속배선 형성방법. While injecting the TEOS gas into the chamber at a flow rate of 50 to 300 kPa, the O 2 gas at a flow rate of 50 to 1000 kPa, and the NH 3 gas at a flow rate of 300 to 3000 kPa, the temperature is 300 to 400 ° C and the pressure is 0.01 to A metal wiring forming method using a dual damascene process characterized in that the deposition to a thickness of 500 ~ 1000Å by PECVD method under the condition of 300 Torr. 하부 금속배선이 형성된 반도체 기판 상에 비아홀용 제1산화막과 식각정지막용 질화막 및 배선용 제2산화막을 차례로 형성하는 단계와, 상기 제2산화막과 질화막 및 제1산화막을 식각하여 하부 금속배선을 노출시키는 비아홀을 형성하는 단계와, 상기 질화막을 식각정지막으로해서 비아홀 상측의 제2산화막 부분을 식각하여 트렌치를 형성하는 단계와, 상기 콘택홀 및 트렌치 내에 금속막을 매립시켜 상부 금속배선을 형성하는 단계를 포함하는 듀얼 다마신 공정을 이용한 금속배선 형성방법에 있어서, Sequentially forming a via hole first oxide film, an etch stop film nitride film, and a wiring second oxide film on the semiconductor substrate on which the lower metal wiring is formed, and etching the second oxide film, the nitride film, and the first oxide film to expose the lower metal wiring. Forming a via hole, etching the second oxide film portion over the via hole by using the nitride film as an etch stop layer, and forming a trench in the contact hole and the trench to form an upper metal wiring; In the metal wiring forming method using a dual damascene process comprising, 상기 질화막은 상기 제1산화막 증착 후에 그 표면을 플라즈마 처리하는 것을 통해 질화(nitridation)시켜 형성하고, 상기 제2산화막은 질화되어 형성된 질화막 상에 증착하며, 상기 제1산화막과 질화막 및 제3산화막은 인-시튜(In-situ) 방식으로 형성하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 금속배선 형성방법. The nitride film is formed by nitriding the surface of the first oxide film through plasma treatment, and the second oxide film is deposited on the nitrided nitride film, and the first oxide film, the nitride film, and the third oxide film are Forming a metal wiring using a dual damascene process, characterized in that formed in-situ (In-situ) method. 제 5 항에 있어서, 상기 플라즈마 처리는The method of claim 5, wherein the plasma treatment NH3 또는 N2O 가스의 유량을 300∼3000㏄로 하면서 파워를 50∼1000W로 하여 10∼120초 동안 수행하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 금속배선 형성방법. A method for forming metal wiring using a dual damascene process, characterized in that the power is set to 50 to 1000 W for 10 to 120 seconds while the flow rate of NH 3 or N 2 O gas is set to 300 to 3000 kPa. 제 5 항에 있어서, 상기 제1 및 제2산화막은 The method of claim 5, wherein the first and second oxide film 챔버 내에 TEOS 가스를 50∼300㏄의 유량, 그리고, O2 가스를 50∼1000㏄의 유량으로 주입하면서, 온도를 300∼400℃, 압력을 0.01∼300Torr로 하는 조건하에서 PECVD 방식에 따라 각각 3000∼4000Å 및 4000∼5000Å의 두께로 증착하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 금속배선 형성방법.While injecting TEOS gas into the chamber at a flow rate of 50 to 300 kPa and O 2 gas at a flow rate of 50 to 1000 kPa, the respective temperatures were 3000 in accordance with the PECVD method under the conditions of 300 to 400 ° C and a pressure of 0.01 to 300 Torr. A metal wiring forming method using a dual damascene process, characterized in that the deposition to a thickness of -4000 kHz and 4000-5000 Å.
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US6340435B1 (en) * 1998-02-11 2002-01-22 Applied Materials, Inc. Integrated low K dielectrics and etch stops
KR20020034352A (en) * 2000-11-01 2002-05-09 윤종용 Method of forming interlayer dielectrics of semiconductor device and method of forming interconnection using the same
KR20020055153A (en) * 2000-12-28 2002-07-08 박종섭 Method for forming metal line using dual damascene
US20040087179A1 (en) * 2002-10-30 2004-05-06 Asm Japan K.K. Method for forming integrated dielectric layers

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US6340435B1 (en) * 1998-02-11 2002-01-22 Applied Materials, Inc. Integrated low K dielectrics and etch stops
KR20020034352A (en) * 2000-11-01 2002-05-09 윤종용 Method of forming interlayer dielectrics of semiconductor device and method of forming interconnection using the same
KR20020055153A (en) * 2000-12-28 2002-07-08 박종섭 Method for forming metal line using dual damascene
US20040087179A1 (en) * 2002-10-30 2004-05-06 Asm Japan K.K. Method for forming integrated dielectric layers

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