KR100728945B1 - A method for fabricating metal line - Google Patents

A method for fabricating metal line Download PDF

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KR100728945B1
KR100728945B1 KR1020010037001A KR20010037001A KR100728945B1 KR 100728945 B1 KR100728945 B1 KR 100728945B1 KR 1020010037001 A KR1020010037001 A KR 1020010037001A KR 20010037001 A KR20010037001 A KR 20010037001A KR 100728945 B1 KR100728945 B1 KR 100728945B1
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metal line
forming
metal
insulating layer
opening
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KR1020010037001A
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KR20030000847A (en
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김정수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 금속라인 간의 연결부분에서 저항 증가로 인한 입출력신호의 속도가 저하되는 것을 방지할 수 있는 금속라인 형성방법에 관해 개시한다.The present invention discloses a method for forming a metal line that can prevent the speed of the input / output signal from being lowered due to an increase in resistance at the connection portion between the metal lines.

개시된 본 발명의 금속라인 형성방법은 반도체기판 상에 제 1금속라인을 형성하는 공정과, 기판 상에 제 1금속라인의 일부를 노출시키는 제 1개구부를 가진 제 1절연층을 형성하는 공정과, 제 1개구부를 덮어 제 1금속라인과 전기적으로 연결되며, 제 1금속라인과 중첩되도록 제 2금속라인을 형성하는 공정과, 제 1절연층 상에 제 2금속라인의 일부를 노출시키는 제 2개구부를 가진 제 2절연층을 형성하는 공정과, 제 2개구부를 덮어 제 2금속라인과 전기적으로 연결되는 제 3금속라인을 형성하는 공정을 포함한다.The disclosed metal line forming method of the present invention comprises the steps of forming a first metal line on a semiconductor substrate, forming a first insulating layer having a first opening for exposing a portion of the first metal line on the substrate; Forming a second metal line to be electrically connected to the first metal line and overlapping the first metal line, and to expose a part of the second metal line on the first insulating layer to cover the first opening. And forming a second metal layer having a second insulating layer, and forming a third metal line electrically connected to the second metal line by covering the second opening.

Description

금속라인의 형성방법{A method for fabricating metal line}A method for fabricating metal line

도 1a 내지 도 1c는 종래기술에 따른 금속라인의 형성을 보인 제조공정도.1a to 1c is a manufacturing process showing the formation of a metal line according to the prior art.

도 2a 내지 도 2d는 본 발명에 따른 금속라인의 형성을 보인 제조공정도.Figure 2a to 2d is a manufacturing process showing the formation of a metal line according to the present invention.

도 3은 본 발명에 따른 제 1금속라인의 평면도.3 is a plan view of a first metal line according to the present invention;

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

200. 반도체기판 202, 212, 230. 금속라인200. Semiconductor substrates 202, 212, 230. Metal lines

204, 214. 절연층 206, 216. 개구부 204, 214. Insulation layer 206, 216. Opening

215. 텅스텐 플러그       215. Tungsten Plug

본 발명은 반도체장치의 형성방법에 관한 것으로, 보다 상세하게는 금속라인(metal line) 간의 연결부분에서 저항 증가로 인해 입출력(input, output)신호의 속도가 저하되는 것을 방지할 수 있는 금속라인 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, to forming a metal line which can prevent the speed of an input / output signal from being lowered due to an increase in resistance at a connection portion between metal lines. It is about a method.

하나의 반도체 칩에는 수 많은 반도체 소자, 예컨대 셀 트랜지스터(cell transistor) 및 셀 캐패시터(capacitor) 등이 형성되어 있다. 그리고 칩안의 셀 영역에서 상기 소자들은 매트릭스(matrix)형태로 배열을 이루고 있고, 각 소자들은 상호연결라인에 의해 연결되어 있다.A number of semiconductor devices, such as cell transistors and cell capacitors, are formed in one semiconductor chip. In the cell region of the chip, the devices are arranged in a matrix, and each device is connected by interconnect lines.

이에 따라, 셀 트랜지스터의 게이트나 셀 캐패시터의 하부 전극 등은 비트 라인(bit line)처럼 하나의 라인을 형성하게 된다. 이와같이, 다양한 형태의 금속라인이 반도체 장치의 제조 과정에서 형성된다.Accordingly, the gate of the cell transistor, the lower electrode of the cell capacitor, or the like forms one line like a bit line. As such, various types of metal lines are formed in the manufacturing process of the semiconductor device.

도 1a 내지 도 1c는 종래기술에 따른 금속라인의 형성을 보인 제조공정도이다.1a to 1c is a manufacturing process showing the formation of a metal line according to the prior art.

종래기술에 따른 금속라인의 형성방법은, 도 1a에 도시된 바와 같이, 반도체기판(100) 상에 텅스텐을 스퍼터링(sputtering)에 의해 증착한 후, 소정형상으로 패턴 식각하여 제 1금속라인(102)을 형성한다. 이때, 제 1금속라인(102)은 1000∼2000Å두께를 가진다.In the method of forming a metal line according to the related art, as shown in FIG. 1A, after depositing tungsten on the semiconductor substrate 100 by sputtering, the pattern is etched into a predetermined shape to form the first metal line 102. ). At this time, the first metal line 102 has a thickness of 1000 to 2000 kPa.

이어서, 반도체기판(100)상에 제 1금속라인(102)을 덮도록 산화막을 화학기상증착하여 제 1절연층(104)을 형성한다.Subsequently, an oxide film is chemically vapor deposited on the semiconductor substrate 100 to cover the first metal line 102 to form the first insulating layer 104.

그 다음, 도 1b에 도시된 바와 같이, 제 1절연층(104)을 식각하여 기판의 일부분을 노출시키는 개구부(106)을 형성한다. Next, as shown in FIG. 1B, the first insulating layer 104 is etched to form an opening 106 that exposes a portion of the substrate.

이 후, 제 1절연층(104) 상에 개구부(106)을 덮도록 텅스텐을 스퍼터링에 의해 증착한 다음, 제 1절연층(104)이 노출되는 시점까지 에치백(etch back)하여 텅스텐 플러그(plug)(105)를 형성한다.Thereafter, tungsten is deposited by sputtering to cover the openings 106 on the first insulating layer 104, and then etched back until the first insulating layer 104 is exposed to form a tungsten plug ( plug 105 is formed.

그리고 제 1절연층(104) 상에 텅스텐 플러그(105)를 덮도록 알루미늄(Al)을 스퍼터링에 의해 증착하여 제 2금속층(108)을 형성한다. 이때, 제 2금속층(108)은 5500∼6500Å두께로 형성한다. In addition, aluminum (Al) is deposited on the first insulating layer 104 to cover the tungsten plug 105 by sputtering to form the second metal layer 108. At this time, the second metal layer 108 is formed to a thickness of 5500 ~ 6500Å.                         

이어서, 도 1c에 도시된 바와 같이, 텅스텐 플러그(105)와 연결되도록 제 2금속층을 패턴 식각하여 제 2금속배선(109)를 형성한다. 이때, 상기 제 2금속배선(109)는 세로방향으로는 제 1금속패턴(109a)이 길게 배열되며, 가로방향으로 제 2금속패턴(109b)이 길게 배열되어져 있다.Subsequently, as shown in FIG. 1C, the second metal layer is pattern-etched to be connected to the tungsten plug 105 to form the second metal wiring 109. In this case, the first metal pattern 109a is elongated in the vertical direction, and the second metal pattern 109b is elongated in the horizontal direction.

이때, 상기 제 1금속패턴(109a)은 인가전압(Vcc)라인이고, 상기 제 2금속패턴(109b)은 입출력(input, output)라인이 된다.In this case, the first metal pattern 109a is an applied voltage Vcc line, and the second metal pattern 109b is an input / output line.

종래의 방법에서는 제 2금속라인(109)을 구성하는 제 1금속패턴(109a)과 제 2금속패턴(109b)이 각각 텅스텐플러그(105)를 통해 제 1금속라인(102)과 전기적으로 연결된다.In the conventional method, the first metal pattern 109a and the second metal pattern 109b constituting the second metal line 109 are electrically connected to the first metal line 102 through the tungsten plug 105, respectively. .

그러나, 종래의 방법에서는 제 1금속라인이 제 2금속라인의 두께에 비해 1/3배 밖에 되질 않기 때문에, 제 1금속라인과 제 2금속라인의 연결부위에서 저항이 크게 증가하여 입출력신호의 속도가 현저히 감소하는 문제점이 발생되었다.However, in the conventional method, since the first metal line is only 1/3 times the thickness of the second metal line, the resistance is greatly increased at the connection portion between the first metal line and the second metal line, thereby increasing the speed of the input / output signal. Significantly reduced problems have occurred.

이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 금속라인의 입출력신호의 속도를 향상시킬 수 있는 금속라인의 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of forming a metal line which can improve the speed of an input / output signal of a metal line.

상기 목적을 달성하기 위한 본 발명의 금속라인의 형성방법은 반도체기판 상에 제 1금속라인을 형성하는 공정과, 기판 상에 제 1금속라인의 일부를 노출시키는 제 1개구부를 가진 제 1절연층을 형성하는 공정과, 제 1개구부를 덮어 제 1금속라 인과 전기적으로 연결되며, 제 1금속라인과 중첩되도록 제 2금속라인을 형성하는 공정과, 제 1절연층 상에 제 2금속라인의 일부를 노출시키는 제 2개구부를 가진 제 2절연층을 형성하는 공정과, 제 2개구부를 덮어 제 2금속라인과 전기적으로 연결되는 제 3금속라인을 형성하는 공정을 포함한 것을 특징으로 한다.The metal line forming method of the present invention for achieving the above object is a first insulating layer having a step of forming a first metal line on a semiconductor substrate and a first opening for exposing a portion of the first metal line on the substrate; Forming a second metal line covering the first opening and electrically connecting with the first metal line, and forming a second metal line to overlap the first metal line; and a part of the second metal line on the first insulating layer. And forming a second insulating layer having a second opening that exposes the second opening, and forming a third metal line that is electrically connected to the second metal line by covering the second opening.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 따른 금속라인의 형성을 보인 제조공정도이고, 도 3은 본 발명에 따른 제 1금속라인의 평면도이다.2a to 2d is a manufacturing process showing the formation of a metal line according to the present invention, Figure 3 is a plan view of a first metal line according to the present invention.

본 발명의 금속라인 형성방법은, 도 2a에 도시된 바와 같이, 먼저, 반도체기판(200) 상에 텅스텐(W)을 스퍼터링에 의해 증착하고 패턴 식각하여 제 1금속라인(202)을 형성한다. 이때, 제 1금속라인(202)은 1000∼2000Å두께로 형성한다.In the metal line forming method of the present invention, as shown in FIG. 2A, first, tungsten (W) is deposited on the semiconductor substrate 200 by sputtering, and the pattern is etched to form the first metal line 202. At this time, the first metal line 202 is formed to a thickness of 1000 ~ 2000Å.

이어서, 기판(200) 상에 제 1금속라인(202)읖 덮도록 산화막을 화학기상증착하여 제 1절연층(204)을 형성한다.Subsequently, an oxide film is chemically vapor deposited so as to cover the first metal line 202 on the substrate 200 to form the first insulating layer 204.

그 다음, 도 2b에 도시된 바와 같이, 제 1절연층(204)을 식각하여 기판(200)의 일부분을 노출시키는 제 1개구부(206)를 형성한다.Next, as shown in FIG. 2B, the first insulating layer 204 is etched to form a first opening 206 exposing a portion of the substrate 200.

상기 제 1개구부(206)는, 도 3에 도시된 바와 같이, 스트라이프(stripe)타입으로 형성시키어 이 후에 형성되는 제 2금속라인이 상기 제 1금속라인(202)과 중첩된 구조를 가질 수 있도록 한다.As shown in FIG. 3, the first opening 206 is formed in a stripe type so that a second metal line formed thereafter may have a structure overlapping with the first metal line 202. do.

이 후, 제 1절연층(204) 상에 텅스텐(W)을 스퍼터링에 의해 증착한 다음, 포 토리쏘그라피에 의해 식각하여 상기 제 1금속라인(202)과 연결되는 제 2금속라인(212)을 형성한다. 이때, 상기 제 2금속라인(212)은 1000∼2000Å두께로 형성한다.Thereafter, tungsten (W) is deposited on the first insulating layer 204 by sputtering, and then etched by photolithography to connect the second metal line 212 connected to the first metal line 202. To form. At this time, the second metal line 212 is formed to a thickness of 1000 ~ 2000Å.

이때, 제 1개구부(206)를 형성하는 공정과 제 2금속라인(212)을 형성하는 공정 사이에, 상기 제 1금속라인(202)을 300Å이내로 오버에치(over etch)하는 공정을 추가함으로써, 제 2금속라인(212)에 대한 제 1금속라인(202)의 부착력을 향상시킬 수 있다.At this time, between the step of forming the first opening 206 and the step of forming the second metal line 212, by adding a step of over-etching the first metal line 202 to within 300 kPa The adhesion of the first metal line 202 to the second metal line 212 may be improved.

이어서, 도 2c에 도시된 바와 같이, 제 1절연층(204) 상에 상기 제 2금속라인(212)을 덮도록 산화막을 화학기상증착하여 제 2절연층(214)을 형성한다.Subsequently, as illustrated in FIG. 2C, an oxide film is chemically vapor deposited on the first insulating layer 204 to cover the second metal line 212 to form a second insulating layer 214.

그 다음, 제 2절연층(214)을 포토리쏘그라피에 의해 식각하여 제 2금속라인(212)의 일부분을 노출시키는 제 2개구부(216)를 형성한다.The second insulating layer 214 is then etched by photolithography to form a second opening 216 exposing a portion of the second metal line 212.

이 후, 도 2d에 도시된 바와 같이, 제 2절연층(214) 상에 제 2개구부(216)을 덮도록 텅스텐을 스퍼터링에 의해 증착한 다음, 제 2절연층(214) 표면이 노출되는 시점까지 에치백하여 텅스텐 플러그(215)를 형성한다.After that, as shown in FIG. 2D, tungsten is deposited by sputtering to cover the second openings 216 on the second insulating layer 214, and then the surface of the second insulating layer 214 is exposed. It is etched back to form a tungsten plug 215.

그 다음, 상기 제 2절연층(214) 상에 텅스텐 플러그(215)을 덮도록 알루미늄(Al)을 스퍼터링에 의해 증착한 다음, 포토리쏘그라피에 의해 식각하여 제 3금속라인(230)을 형성한다. 이때, 제 3금속라인(230)은 5500∼6500Å두께로 형성한다.Next, aluminum (Al) is deposited on the second insulating layer 214 to cover the tungsten plug 215 by sputtering, and then etched by photolithography to form a third metal line 230. . At this time, the third metal line 230 is formed to a thickness of 5500 ~ 6500Å.

상기 제 3금속라인(230)은 세로방향으로는 제 1금속패턴(230a)이 길게 배열되며, 가로방향으로는 제 2금속패턴(230b)이 길게 배열되어져 있다. 이때, 상기 제 1금속패턴(230a)은 인가전압(Vcc)라인이고, 제 2금속패턴(230b)은 입출력라인이 된다.In the third metal line 230, the first metal pattern 230a is elongated in the vertical direction, and the second metal pattern 230b is elongated in the horizontal direction. In this case, the first metal pattern 230a is an applied voltage Vcc line, and the second metal pattern 230b is an input / output line.

또한, 상기 제 3금속라인(230)의 제 1금속패턴(230a)과 제 2금속패턴(230b)은 텅스텐 플러그(215)를 통해 제 2금속라인(212)과 전기적으로 연결되며, 상기 제 1개구부를 통해 제 1금속라인(202)과도 전기적으로 연결된 구조를 가진다.In addition, the first metal pattern 230a and the second metal pattern 230b of the third metal line 230 are electrically connected to the second metal line 212 through the tungsten plug 215. It also has a structure electrically connected to the first metal line 202 through the opening.

본 발명의 금속라인 형성방법은 제 2금속라인 하부에 제 2금속라인과 중첩된 구조를 갖도록 제 1금속라인을 형성함으로써, 제 3금속라인과의 전기적 연결 시에 제 2금속라인의 두께를 증가시키지 않고서도 제 2금속라인의 저항이 증가되는 것을 방지할 수 있다. 따라서, 본 발명에서는 제 3금속라인을 구성하는 제 2금속패턴의 입출력신호의 속도가 감소되는 것이 방지된다.In the metal line forming method of the present invention, the first metal line is formed under the second metal line to have a structure overlapping with the second metal line, thereby increasing the thickness of the second metal line during electrical connection with the third metal line. Without increasing the resistance of the second metal line can be prevented. Therefore, in the present invention, the speed of the input / output signal of the second metal pattern constituting the third metal line is prevented from being reduced.

이상에서와 같이, 본 발명의 금속라인 형성방법에서는 제 2금속라인 하부에 제 2금속라인과 중첩된 구조를 갖도록 제 1금속라인을 형성함으로써, 제 3금속라인과의 전기적 연결 시에 제 2금속라인의 저항이 증가되는 것을 방지할 수 있으며, 또한 입출력신호의 속도를 증가시키기 위해 별도로 제 2금속라인의 두께를 증가시키는 공정이 필요치 않으므로, 두께 증가에 따른 브릿지(bridge)가 발생될 우려가 없다. As described above, in the metal line forming method of the present invention, by forming the first metal line to have a structure overlapping with the second metal line under the second metal line, the second metal at the time of electrical connection with the third metal line Since the resistance of the line can be prevented from increasing and the process of increasing the thickness of the second metal line is not necessary in order to increase the speed of the input / output signal, there is no fear of generating a bridge due to the increase of the thickness. .

따라서, 본 발명의 방법을 통해 제 3금속라인을 구성하는 제 2금속패턴의 입출력신호의 속도가 감소되는 것이 방지할 수 있으므로, 제품의 신뢰성을 향상시킬 수 있다. Therefore, the speed of the input / output signal of the second metal pattern constituting the third metal line can be prevented from being reduced by the method of the present invention, thereby improving the reliability of the product.                     

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (3)

반도체기판 상에 제 1금속라인을 형성하는 공정과,Forming a first metal line on the semiconductor substrate; 상기 기판 상에 상기 제 1금속라인의 일부를 노출시키는 제 1개구부를 가진 제 1절연층을 형성하는 공정과,Forming a first insulating layer having a first opening for exposing a portion of the first metal line on the substrate; 상기 제 1개구부를 덮어 상기 제 1금속라인과 전기적으로 연결되며, 상기 제 1금속라인과 중첩되도록 제 2금속라인을 형성하는 공정과,Forming a second metal line covering the first opening and electrically connected to the first metal line and overlapping the first metal line; 상기 제 1절연층 상에 상기 제 2금속라인의 일부를 노출시키는 제 2개구부를 가진 제 2절연층을 형성하는 공정과,Forming a second insulating layer having a second opening on the first insulating layer to expose a portion of the second metal line; 상기 제 2개구부를 덮어 상기 제 2금속라인과 전기적으로 연결되는 제 3금속라인을 형성하는 공정을 포함한 것을 특징으로 하는 금속라인의 형성방법.And forming a third metal line covering the second opening and electrically connecting the second metal line. 제 1항에 있어서, 상기 제 1금속라인 및 상기 제 2금속라인은 1000∼2000Å두께로 형성하는 것을 특징으로 하는 금속라인의 형성방법.The method of claim 1, wherein the first metal line and the second metal line are formed to have a thickness of 1000 to 2000 microns. 제 1항에 있어서, 상기 제 1절연층 형성 공정과 상기 제 2금속라인 형성 공정 사이에, 상기 제 1금속라인을 300Å이내로 오버에치하는 공정을 추가하는 것을 특징으로 하는 금속라인의 형성방법.2. The method of claim 1, further comprising: overetching the first metal line to within 300 mV between the first insulating layer forming step and the second metal line forming step.
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JPH01143335A (en) * 1987-11-30 1989-06-05 Matsushita Electron Corp Resistance measuring element
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