KR100248805B1 - A method for forming metal wire in semiconductor device - Google Patents
A method for forming metal wire in semiconductor device Download PDFInfo
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- KR100248805B1 KR100248805B1 KR1019960076283A KR19960076283A KR100248805B1 KR 100248805 B1 KR100248805 B1 KR 100248805B1 KR 1019960076283 A KR1019960076283 A KR 1019960076283A KR 19960076283 A KR19960076283 A KR 19960076283A KR 100248805 B1 KR100248805 B1 KR 100248805B1
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- Prior art keywords
- forming
- semiconductor device
- lower metal
- contact
- via hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 장치 제조방법Semiconductor device manufacturing method
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
반도체 장치의 고집적화와 더불어 비아홀의 크기는 점차 줄고 있으며, 이에 따라 비아 콘택의 접촉 저항이 높아진다. 이러한, 접촉 저항의 증가는 반도체 장치의 동작 속도 등의 특성을 저하시키는 요인이 되는 문제점이 있었음.With the higher integration of semiconductor devices, the size of the via hole is gradually decreasing, thereby increasing the contact resistance of the via contact. Such an increase in contact resistance has a problem of causing deterioration of characteristics such as operating speed of the semiconductor device.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 발명은 하부 금속 배선 상에 콘택되는 비아홀을 형성한 후, 소정 두께만큼 식각하여 상부 금속막과 하부 금속막의 접촉 면적을 증가시킴으로써 접촉 저항을 감소시키는 반도체 장치의 비아 콘택 형성 방법을 제공하고자 함.The present invention is to provide a method for forming a via contact in a semiconductor device which reduces contact resistance by forming a via hole contacted on a lower metal wiring, and then etching by a predetermined thickness to increase the contact area between the upper metal layer and the lower metal layer.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 장치의 비아 콘택 형성에 이용됨.Used to form via contacts in semiconductor devices.
Description
본 발명은 반도체 장치의 금속 배선 간의 전기적 연결을 위한 비아 콘택(via contact) 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a via contact for electrical connection between metal wires of a semiconductor device.
반도체 장치의 고집적화와 더불어 비아홀의 크기는 점차 줄어가고 있다. 이에 따라, 비아 콘택의 접촉 저항이 높아지게 된다. 즉, 비아홀 크기의 감소에 따라 금속 배선 간의 접촉 면적이 줄어들고, 접촉 저항 역시 증가하게 되는 것이다.With high integration of semiconductor devices, the size of via holes is gradually decreasing. As a result, the contact resistance of the via contact becomes high. In other words, as the via hole size decreases, the contact area between the metal wires decreases, and the contact resistance also increases.
이러한, 접촉 저항의 증가는 반도체 장치의 동작 속도 등의 특성을 저하시키는 요인이 된다.Such an increase in contact resistance is a factor that lowers characteristics such as the operating speed of the semiconductor device.
본 발명은 비아홀 크기의 변화 없이 하부 금속막의 접촉 면적을 증가시킴으로써 접촉 저항을 감소시키는 반도체 장치의 비아 콘택 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a via contact of a semiconductor device which reduces contact resistance by increasing the contact area of the lower metal film without changing the via hole size.
도 1a 내지 도 1d는 본 발명의 일실시예에 따른 반도체 장치의 비아 콘택 형성 공정도.1A to 1D are diagrams illustrating a via contact forming process of a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 하부층 11 : 하부 금속막10: lower layer 11: lower metal film
11a : 하부 금속 배선 12 : 포토레지스트 패턴11a: lower metal wiring 12: photoresist pattern
13 : 층간 절연막 14 : 상부 금속막13 interlayer insulation film 14 upper metal film
상기와 같은 목적을 달성하기 위하여 본 발명은 반도체 기판 상에 형성된 소정의 하부층 상부에 하부 금속막을 형성하는 단계, 상기 하부 금속막 상부에 비아홀 형성 부위의 단면이 凹 형상인 포토레지스트 패턴을 형성하는 단계, 상기 포토레지스트 패턴을 식각 장벽으로 하여 상기 하부 금속막을 식각함으로써 비아홀 형성부위의 단면이 凹 형상인 하부 금속 배선을 형성하는 단계, 전체구조 상부에 층간 절연막을 형성하고, 상기 비아홀 형성 부위에 비아홀을 형성하는 단계 및 전체구조 상부에 상기 하부 금속 배선에 콘택되는 상부 금속막을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention includes forming a lower metal film on a predetermined lower layer formed on a semiconductor substrate, and forming a photoresist pattern having a cross-sectional shape of a via hole forming portion on the lower metal film. And etching the lower metal layer using the photoresist pattern as an etch barrier to form a lower metal interconnection having a sectional shape of the via hole forming portion, forming an interlayer insulating layer on the entire structure, and forming a via hole in the via hole forming portion. And forming an upper metal film contacting the lower metal wire on the entire structure.
이하, 첨부된 도면 도 1a 내지 도 1d를 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 1A to 1D.
먼저, 도 1a에 도시된 바와 같이 실리콘 기판 상에 형성된 소정의 하부층(10) 상부에 하부 금속막(11)을 형성하고, 그 상부에 포토레지스트를 도포하고, 금속 배선 형성을 위한 포토레지스트 패턴(12)을 비아 콘택이 형성될 부위에서 그 단면의 중앙부가 오목한 凹 형상으로 형성한다. 이때, 포토레지스트 패턴(12)의 형상은 노광 및 현상시의 부분별 차이에 의해 그 중앙부의 포토레지스트가 완전히 제거되지 않고 남음으로써 형성할 수 있다. 그리고, 비아 콘택이 형성될 부위 이외의 영역에서는 점선과 같이 정상적인 패턴으로 형성된다.First, as shown in FIG. 1A, a lower metal layer 11 is formed on a predetermined lower layer 10 formed on a silicon substrate, a photoresist is coated on the upper layer, and a photoresist pattern for forming metal wiring ( 12) is formed in a concave 凹 shape at the center of the cross section at the portion where the via contact is to be formed. At this time, the shape of the photoresist pattern 12 can be formed by remaining the photoresist at the center portion thereof without being completely removed due to the difference in portions during exposure and development. The regions other than the portion where the via contact is to be formed are formed in a normal pattern such as a dotted line.
다음으로, 도 1b에 도시된 바와 같이 상기한 포토레지스트 패턴(12)을 식각장벽으로 하여 하부 금속막(11)을 선택적 식각한다. 이때, 형성되는 하부 금속 배선(11a)은 상기한 포토레지스트 패턴(12)와 같은 형상으로 형성된다. 즉, 비아 콘택이 형성될 부위에서 그 단면의 중앙부가 凹 형상으로, 그 나머지 부분에서는 점선과 같이 정상적인 패턴으로 형성된다. 이때, 하부 금속 배선(11a) 중앙부의 부분식각된 깊이는 약 500Å 내지 약 200Å 정도이다.Next, as shown in FIG. 1B, the lower metal layer 11 is selectively etched using the photoresist pattern 12 as an etch barrier. At this time, the lower metal wiring 11a to be formed is formed in the same shape as the photoresist pattern 12 described above. That is, in the portion where the via contact is to be formed, the center portion of the cross section is formed in a 凹 shape, and the remaining portion is formed in a normal pattern like a dotted line. At this time, the partially etched depth of the central portion of the lower metal wiring 11a is about 500 kPa to about 200 kPa.
이어서, 도 1c에 도시된 바와 같이 전체구조 상부에 층간 졀연막(13)을 증착하고, 전체구조 상부에 포토레지스트를 형성하고, 비아홀 형성을 위한 포토레지스트 패턴을 형성한 다음, 습식 및 건식 식각을 실시하여 미리 예정된 부위에 콘택홀을 형성한다.Subsequently, as shown in FIG. 1C, an interlayer dielectric film 13 is deposited on the entire structure, a photoresist is formed on the entire structure, a photoresist pattern for forming a via hole is formed, and wet and dry etching are performed. To form a contact hole in a predetermined area.
끝으로, 도 1d에 도시된 바와 같이 전체구조 상부에 상부 금속막(14)을 증착함으로써 이층 구조의 금속 배선 및 비아 콘택 형성을 완료한다.Finally, as shown in FIG. 1D, the upper metal film 14 is deposited on the entire structure to complete the formation of the metal wiring and the via contact of the two-layer structure.
상기와 같은 본 발명의 일실시예에 나타낸 바와 같이 본 발명을 실시하면 비아홀의 크기를 줄이지 않고, 접촉 면적을 늘임으로써 비아 콘택의 접촉 저항을 감소시킬 수 있다.As shown in an embodiment of the present invention as described above, the contact resistance of the via contact can be reduced by increasing the contact area without reducing the size of the via hole.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기한 바와 같이 본 발명은 비아홀의 크기를 줄이지 않고, 접촉 면적을 늘임으로써 비아 콘택의 접촉 저항을 감소시키게 되어, 반도체 장치의 고집적화에 기여하는 효과가 있으며, 반도체 장치 자체의 동작 특성 향상을 기대할 수 있다.As described above, the present invention reduces the contact resistance of the via contact by increasing the contact area without reducing the size of the via hole, thereby contributing to the high integration of the semiconductor device, and improving the operating characteristics of the semiconductor device itself. have.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960076283A KR100248805B1 (en) | 1996-12-30 | 1996-12-30 | A method for forming metal wire in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960076283A KR100248805B1 (en) | 1996-12-30 | 1996-12-30 | A method for forming metal wire in semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR19980057013A KR19980057013A (en) | 1998-09-25 |
| KR100248805B1 true KR100248805B1 (en) | 2000-03-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019960076283A KR100248805B1 (en) | 1996-12-30 | 1996-12-30 | A method for forming metal wire in semiconductor device |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05109905A (en) * | 1991-10-15 | 1993-04-30 | Fujitsu Ltd | Semiconductor device and its production |
| JPH0621235A (en) * | 1992-07-01 | 1994-01-28 | Nec Corp | Semiconductor device |
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1996
- 1996-12-30 KR KR1019960076283A patent/KR100248805B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05109905A (en) * | 1991-10-15 | 1993-04-30 | Fujitsu Ltd | Semiconductor device and its production |
| JPH0621235A (en) * | 1992-07-01 | 1994-01-28 | Nec Corp | Semiconductor device |
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| Publication number | Publication date |
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| KR19980057013A (en) | 1998-09-25 |
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