KR100630567B1 - Method for removing the fuse oxide - Google Patents

Method for removing the fuse oxide Download PDF

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KR100630567B1
KR100630567B1 KR1020040115627A KR20040115627A KR100630567B1 KR 100630567 B1 KR100630567 B1 KR 100630567B1 KR 1020040115627 A KR1020040115627 A KR 1020040115627A KR 20040115627 A KR20040115627 A KR 20040115627A KR 100630567 B1 KR100630567 B1 KR 100630567B1
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fuse
photoresist
oxide film
pad portion
sulfuric acid
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KR20060076996A (en
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김형석
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

본 발명은 퓨즈 산화막 제거 방법에 관한 것으로, 포토레지스트를 도포하는 단계; 마스크를 이용하여 상기 포토레지스트를 노광 현상함으로써, 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 마스크로 퓨즈 금속막과 패드 부분을 동시에 식각한 후, 상기 포토레지스트를 제거하는 단계; 상기 포토레지스트 제거 후, 황산 처리와 탈이온수로 세척하는 단계 및 솔벤트로 세척하는 단계를 포함하여 이루어짐에 기술적 특징이 있고, 절연막 식각시 퓨즈 금속막과 패드 부분을 동시에 식각하고, 포토 공정을 한 후, 황산을 이용함으로써 수율이 향상하고, 웨이퍼의 신뢰성이 향상하는 효과가 있다.The present invention relates to a method for removing a fuse oxide film, the method comprising: applying a photoresist; Exposing and developing the photoresist using a mask to form a pattern; Simultaneously etching the fuse metal layer and the pad portion using the photoresist pattern as a mask, and then removing the photoresist; After removing the photoresist, there is a technical feature, including the step of washing with sulfuric acid treatment and deionized water and the step of washing with solvent, and simultaneously etching the fuse metal film and the pad portion during the etching of the insulating film, after the photo process By using sulfuric acid, the yield is improved and the reliability of the wafer is improved.

퓨즈, 산화막Fuse, oxide film

Description

퓨즈 산화막 제거 방법{Method for removing the fuse oxide} Method for removing the fuse oxide             

도 1a 내지 도 1c는 종래의 퓨즈 산화막 제거 방법을 나타내는 공정 단면도이다.1A to 1C are cross-sectional views illustrating a conventional method for removing a fuse oxide film.

도 2a는 본 발명의 패드 부분과 퓨즈 금속막을 동시에 식각하는 것을 나타내는 단면도이다.2A is a cross-sectional view illustrating etching of a pad portion and a fuse metal film at the same time.

도 2b 내지 도 2d는 본 발명에 의한 퓨즈 산화막 제거 방법을 나타내는 공정 단면도이다.2B to 2D are cross-sectional views illustrating a method of removing a fuse oxide film according to the present invention.

본 발명은 퓨즈 산화막 제거 방법에 관한 것으로, 보다 자세하게는 황산을 이용하여 질산티타늄을 제거할 수 있는 퓨즈 산화막 제거 방법에 관한 것이다.The present invention relates to a method for removing a fuse oxide film, and more particularly, to a method for removing a fuse oxide film by using titanium sulfate to remove titanium nitrate.

반도체 복합 소자나 메모리 소자를 구성하는 수많은 미세 셀(cell) 중에서 결함이 한 개라도 있으면 메모리로서의 제구실을 하지 못하므로 불량품으로 처리된다. 하지만 메모리 내의 일부 셀에만 결함이 발생하였는데도 불구하고 소자 전체를 불량품으로 폐기하는 것은 수율을 낮추는 비효율적인 처리 방법이다.If any defect is found among the many fine cells constituting the semiconductor composite element or the memory element, it cannot be treated as a memory and thus is treated as a defective product. However, even though only a few cells in the memory have failed, discarding the entire device as defective is an inefficient way to reduce yield.

따라서, 현재는 메모리 셀(일명, 용장형 셀이라 한다) 내에 미리 설치해둔 예비 메모리 셀을 이용하여 불량 셀을 대체함으로써, 전체 메모리를 되살려 주는 방식으로 수율 향상을 이루고 있다.Accordingly, the yield improvement is achieved by replacing the defective cells by using spare memory cells pre-installed in the memory cells (also called redundant cells).

용장형 셀을 이용한 리페어 작업은 통상, 일정 셀 어레이(cell array) 마다 스페어 로우(spare Row)와 스페어 컬럼(spare column)을 미리 설치해 두어 결함이 발생된 불량 메모리 셀을 로우/칼럼 단위로 스페어 메모리 셀로 치환해 주는 방식으로 진행된다.In the repair operation using redundant cells, spare rows and spare columns are pre-installed for each cell array so that defective memory cells having defects are stored in row / column units. It proceeds by replacing it with a cell.

즉, 웨이퍼 가공 완료후 테스트를 통해 불량 메모리 셀을 골라내면 그에 해당하는 어드레스(address)를 스페어 셀의 어드레스 신호로 바꾸어 주는 프로그램을 내부회로에 행하게 된다. 따라서, 실제 사용시에 불량 라인에 해당하는 어드레스 신호가 입력되면 이 대신 예비 라인으로 선택이 바뀌게 되는 것이다. 이 프로그램 방식 중의 하나가 바로 레이저 빔으로 퓨즈를 태워 끊어버리는 방식인데, 이러한 퓨즈 재료로는 주로 금속막이 이용되고 있다.In other words, when a defective memory cell is selected through a test after wafer processing is completed, a program is executed in the internal circuit to replace the corresponding address with the address signal of the spare cell. Therefore, when an address signal corresponding to a bad line is input in actual use, the selection is switched to a spare line instead. One of the programming methods is a method of burning a fuse with a laser beam, and a metal film is mainly used as the fuse material.

레이저 빔으로 퓨즈를 끊기 위해서는 퓨즈 상단의 잔존 산화막 두께를 일정하게 유지하는 것이 중요하며, 이는 상기 잔존 산화막의 두께가 기설정치보다 두껍거나 얇으면 레이저 빔의 난반사에 의해 퓨즈 커팅(cutting)이 제대로 이루어지지 않게 되어 용장형 셀이 리페어 기능을 수행할 수 없기 때문이다.It is important to keep the remaining oxide thickness at the top of the fuse constant in order to blow the fuse with the laser beam. If the thickness of the remaining oxide film is thicker or thinner than the preset value, the fuse is cut properly by the diffuse reflection of the laser beam. This is because the redundant cells cannot perform the repair function.

도 1a 내지 도 1c는 종래의 퓨즈 산화막 제거 방법을 나타내는 공정 단면도이다. 도 1a 내지 도 1c에 도시된 바와 같이, 절연막(10)을 식각함과 동시에 레이 저 리페어(Laser Repair)를 위한 퓨즈 금속막(20) 위의 산화막을 제어해야 한다.1A to 1C are cross-sectional views illustrating a conventional method for removing a fuse oxide film. As shown in FIGS. 1A to 1C, the oxide film on the fuse metal film 20 for laser repair should be controlled while the insulating film 10 is etched.

상기 퓨즈 금속막(20) 위의 산화막을 남기는 이유는 퓨즈 리페어시 커팅(Cutting) 능력을 향상시키고, 상기 커팅시 발생하는 파티클(Particle) 등을 최소화하기 위해 단단한 산화막을 이용하게 된다.The reason for leaving the oxide layer on the fuse metal layer 20 is to use a hard oxide layer to improve the cutting ability during the fuse repair and to minimize the particles generated during the cutting.

그러나 절연막(10)을 식각시 산화막을 동시에 제어하는 과정에서 패드 부분(30)에 상부 질화티타늄(TiN)(40)이 남거나 상기 상부 질화티타늄(40)을 모두 제거하기 위해 건식 식각을 한다. 이때, 건식 식각을 많이 하면 상기 퓨즈 금속막(20) 위의 산화막이 모두 제거되는 문제가 발생하게 된다.However, in the process of simultaneously controlling the oxide film when the insulating film 10 is etched, the upper titanium nitride (TiN) 40 remains on the pad portion 30 or dry etching is performed to remove all of the upper titanium nitride 40. In this case, if the dry etching is performed a lot, a problem occurs that all of the oxide film on the fuse metal film 20 is removed.

따라서, 패드 부분(30)의 상부 질화티타늄(40)과 퓨즈 금속막(20)의 산화막을 동시에 제어하기는 쉽지 않다.Therefore, it is not easy to simultaneously control the upper titanium nitride 40 of the pad portion 30 and the oxide film of the fuse metal film 20.

그래서 종래의 기술에서는 절연막과 퓨즈 금속막의 식각을 동시에 진행한 후, 포토레지스트를 제거하고, 솔벤트 세정 공정을 진행한다. Therefore, in the related art, the etching of the insulating film and the fuse metal film is simultaneously performed, the photoresist is removed, and the solvent cleaning process is performed.

상기와 같은 종래의 방법은 패드 부분에 질화티타늄이 남아 있어 패드 본딩시 문제를 일으키거나 출하검사(Out-Going Inspection)시 결함으로 인식되어 웨이퍼를 스크랩(Scrap)하는 경우가 발생하고, 퓨즈 금속막 측벽의 금속 폴리머(Metallic Polymer)를 제거하기 어려운 문제점이 있었다.In the conventional method, titanium nitride remains in the pad portion, causing problems in pad bonding or scraping the wafer because it is recognized as a defect during out-going inspection. There was a problem that it is difficult to remove the metal polymer (Metallic Polymer) of the side wall.

따라서, 본 발명은 상기와 같은 종래 기술의 제반 단점과 문제점을 해결하기 위한 것으로, 절연막 식각시 퓨즈 금속막과 패드 부분을 동시에 식각하고, 포토 공 정을 한 후, 황산을 이용하여 질산티타늄을 제거할 수 있는 퓨즈 산화막 제거 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve all the disadvantages and problems of the prior art as described above, after etching the fuse metal film and the pad portion at the same time during the insulating film etching, after the photo process, using titanium sulfate to remove titanium nitrate SUMMARY OF THE INVENTION An object of the present invention is to provide a method for removing a fuse oxide film.

본 발명의 상기 목적은 포토레지스트를 도포하는 단계; 마스크를 이용하여 상기 포토레지스트를 노광 현상함으로써, 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 마스크로 퓨즈 금속막과 패드 부분을 동시에 식각한 후, 상기 포토레지스트를 제거하는 단계; 상기 포토레지스트 제거 후, 황산 처리와 탈이온수로 세척하는 단계 및 솔벤트로 세척하는 단계를 포함하여 이루어진 퓨즈 산화막 제거 방법에 의해 달성된다.The object of the present invention is to apply a photoresist; Exposing and developing the photoresist using a mask to form a pattern; Simultaneously etching the fuse metal layer and the pad portion using the photoresist pattern as a mask, and then removing the photoresist; After removal of the photoresist, it is achieved by a method of removing the oxide oxide film comprising a step of washing with sulfuric acid treatment and deionized water and the step of washing with solvent.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

도 2a는 본 발명의 패드 부분과 퓨즈 금속막을 동시에 식각하는 것을 나타내는 단면도이고, 도 2b 내지 도 2d는 본 발명에 의한 퓨즈 산화막 제거 방법을 나타내는 공정 단면도이다. 도 2a 내지 도 2d에 도시된 바와 같이, 포토레지스트를 도포하고, 마스크를 이용하여 상기 포토레지스트를 노광 현상함으로써, 패턴을 형성한다. 상기 포토레지스트 패턴을 마스크로 퓨즈 금속막(100)과 패드 부분(110)을 동시에 식각한 후, 상기 포토레지스트(120)를 제거한다. 2A is a cross-sectional view showing etching of a pad portion and a fuse metal film at the same time of the present invention, and FIGS. 2B to 2D are cross-sectional views showing a method of removing a fuse oxide film according to the present invention. As shown in Figs. 2A to 2D, a pattern is formed by applying photoresist and exposing and developing the photoresist using a mask. After etching the fuse metal layer 100 and the pad portion 110 using the photoresist pattern as a mask, the photoresist 120 is removed.

다음으로 세정 공정을 진행하는데, 먼저, 황산(H2SO4) 처리 공정을 통해 패드 부분(110)의 질화티타늄(130)을 제거한다. 상기 황산 처리 공정은 약 500Å의 두께로 100% 식각한다. 이후, 탈이온수로 세척 공정을 하고, 마지막으로 솔벤트(Solvent) 세척 공정을 한다.Next, a cleaning process is performed. First, the titanium nitride 130 of the pad portion 110 is removed through a sulfuric acid (H 2 SO 4 ) treatment process. The sulfuric acid treatment process is 100% etched to a thickness of about 500 kPa. Thereafter, the washing process is performed with deionized water, and finally, the solvent washing process is performed.

이때, 상기 황산 처리 공정에 의해 금속 폴리머도 제거된다.At this time, the metal polymer is also removed by the sulfuric acid treatment step.

따라서, 본 발명에 의한 공정을 진행하면 안정적으로 퓨즈 산화막을 제거할 수 있고, 패드 부분을 본딩할 시 상기 패드 부분의 질화티타늄이 제거되어 손쉬운 본딩을 할 수 있으며, 금속 폴리머를 황산처리 후 제거되어, 소자의 수율과 신뢰성이 향상된다.Therefore, the process according to the present invention can stably remove the fuse oxide film, when bonding the pad portion can be easily bonded by removing the titanium nitride of the pad portion, the metal polymer is removed after the sulfuric acid treatment The yield and reliability of the device are improved.

본 발명은 이상에서 살펴본 바와 같이 바람직한 실시예를 들어 도시하고 설명하였으나, 상기한 실시예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

따라서, 본 발명의 퓨즈 산화막 제거 방법은 절연막 식각시 퓨즈 금속막과 패드 부분을 동시에 식각하고, 포토 공정을 한 후, 황산을 이용함으로써 수율이 향상하고, 웨이퍼의 신뢰성이 향상하는 효과가 있다.Therefore, the method of removing the fuse oxide film according to the present invention has the effect of improving the yield and improving the reliability of the wafer by simultaneously etching the fuse metal film and the pad portion during the insulating film etching, performing the photo process, and using sulfuric acid.

Claims (3)

퓨즈 산화막 제거 방법에 있어서,In the fuse oxide film removal method, 포토레지스트를 도포하는 단계;Applying a photoresist; 마스크를 이용하여 상기 포토레지스트를 노광 현상함으로써, 패턴을 형성하는 단계;Exposing and developing the photoresist using a mask to form a pattern; 상기 포토레지스트 패턴을 마스크로 퓨즈 금속막과 패드 부분을 동시에 식각한 후, 상기 포토레지스트를 제거하는 단계; Simultaneously etching the fuse metal layer and the pad portion using the photoresist pattern as a mask, and then removing the photoresist; 상기 포토레지스트 제거 후, 황산 처리로 상기 패드에 형성된 금속 폴리머 제거 및 탈이온수로 세척하는 단계; 및Removing the photoresist, removing the metal polymer formed on the pad by sulfuric acid and washing with deionized water; And 솔벤트로 세척하는 단계를 포함하여 이루어짐을 특징으로 하는 퓨즈 산화막 제거 방법.Fuse oxide removal method comprising the step of washing with a solvent. 제 1항에 있어서,The method of claim 1, 상기 황산 처리는 질화티타늄을 약 500Å의 두께로 100% 식각하는 것을 특징으로 하는 퓨즈 산화막 제거 방법.The sulfuric acid treatment is a method for removing the oxide oxide of the titanium nitride 100% to a thickness of about 500 kW. 삭제delete
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