KR100486874B1 - Bit line formation method of semiconductor device - Google Patents

Bit line formation method of semiconductor device Download PDF

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KR100486874B1
KR100486874B1 KR10-1998-0025660A KR19980025660A KR100486874B1 KR 100486874 B1 KR100486874 B1 KR 100486874B1 KR 19980025660 A KR19980025660 A KR 19980025660A KR 100486874 B1 KR100486874 B1 KR 100486874B1
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titanium
forming
bit line
insulating film
annealing process
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KR10-1998-0025660A
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KR20000004230A (en
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문영화
김춘환
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • General Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 반도체 소자의 비트라인 형성 방법에 관한 것임.The present invention relates to a method for forming a bit line of a semiconductor device.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

티타늄/티타늄 나이트라이드/텅스텐/반사 방지막의 구조를 갖는 비트라인을 형성할 경우, 플러그 폴리실리콘과 비트라인 하부의 티타늄이 반응하여 티타늄 실리사이드(TiSi2)가 생성되는데, 콘택 홀 저부에서 티타늄 실리사이드(TiSi2)가 과도하게 응집될 경우 콘택 저항이 증가하여 소자의 전기적 특성이 저하되는 문제점을 해결하기 위함.When forming a bit line having a structure of titanium / titanium nitride / tungsten / anti-reflective film, the plug polysilicon and the titanium under the bit line react to form titanium silicide (TiSi 2 ), and the titanium silicide ( When TiSi 2 ) is excessively aggregated, the contact resistance is increased to solve the problem of deteriorating the electrical characteristics of the device.

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

비트라인용 콘택 홀 형성 후 티타늄을 증착하고 어닐링하므로써 플러그 폴리실리콘 상부에 균일한 분포를 갖도록 티타늄 실리사이드(TiSi2)를 형성하여 폴리실리콘과 티타늄막 간의 확산 방지층으로 사용되도록 하고, 선택적 에치 백(etch back) 공정으로 반응하지 않은 티타늄(Ti)을 제거한 후, 장벽층을 형성하고 비트라인을 형성함.Titanium is deposited and annealed after forming the bit line to form a titanium silicide (TiSi 2 ) to have a uniform distribution on the top of the plug polysilicon to be used as a diffusion barrier layer between the polysilicon and the titanium film. back) After removing unreacted titanium (Ti), barrier layer is formed and bit line is formed.

Description

반도체 소자의 비트라인 형성 방법Bit line formation method of semiconductor device

본 발명은 반도체 소자의 비트라인 형성 방법에 관한 것으로, 특히 텅스텐 비트라인 형성 방법에 관한 것이다.The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly to a method for forming a tungsten bit line.

현재 반도체 소자의 비트라인은 폴리실리콘/텅스텐 실리사이드의 폴리사이드 구조가 보편적으로 사용되고 있다. 그러나, 이러한 구조의 비트라인은 64M DRAM급 이상에서는 폴리사이드 구조의 높은 면저항으로 인하여 소자의 신호 전달 속도가 지연되는 단점이 있어, 금속 비트라인의 도입이 필요하게 되었다. 최근, 가장 널리 사용되는 금속 비트라인은 텅스텐 비트라인이다.Currently, the polyline structure of polysilicon / tungsten silicide is commonly used as a bit line of a semiconductor device. However, the bit line of such a structure has a disadvantage in that the signal transmission speed of the device is delayed due to the high sheet resistance of the polyside structure at 64M DRAM or higher, and thus, the introduction of the metal bit line is required. Recently, the most widely used metal bitline is tungsten bitline.

도 1은 종래 반도체 소자의 비트라인 형성 방법을 설명하기 위해 도시한 소자의 단면도이다.1 is a cross-sectional view of a device for explaining a method of forming a bit line of a conventional semiconductor device.

소오스(S) 및 드레인(D)이 형성된 반도체 기판(11) 상부에 게이트 전극(12)을 형성한 다음, 층간 절연막을 형성하고 게이트 전극(12) 양측부 및 상부에만 층간 절연막(13)이 잔류하도록 식각 공정을 실시한다. 이후, 전체 구조 상부에 제 1 절연막(14)을 형성하고 플러그 폴리실리콘 형성을 위한 콘택 홀을 형성한다.After the gate electrode 12 is formed on the semiconductor substrate 11 on which the source S and the drain D are formed, an interlayer insulating layer is formed, and the interlayer insulating layer 13 remains only on both sides and the upper portion of the gate electrode 12. The etching process is performed. Thereafter, the first insulating layer 14 is formed on the entire structure, and contact holes for forming plug polysilicon are formed.

다음에, 전체 구조 상부에 폴리실리콘을 증착한 후 플러그용 콘택 홀이 매립되도록 식각 공정을 실시한다. 이후, 전체 구조 상부에 제 2 절연막을 형성한 후 비트라인용 콘택 홀을 형성한다.Next, after the polysilicon is deposited on the entire structure, an etching process is performed to fill the contact holes for plugs. Thereafter, a second insulating film is formed on the entire structure, and then a bit line contact hole is formed.

그리고, 콘택 홀을 포함한 전체 구조 상부에 티타늄/티타늄 나이트라이드/텅스텐/반사 방지막 구조를 갖는 비트라인(17, 18)을 형성한다. 이때, 비트라인을 구성하는 하부층인 티타늄막(17)의 티타늄과 플러그 폴리실리콘층(15)의 폴리실리콘이 반응하여 티타늄 실리사이드막(TiSi2; 19)이 형성된다. 그런데, 이 티타늄 실리사이드막(19)이 균일하게 형성되지 않고, 비트라인 형성용 콘택 홀 저부에 과도하게 응집(A 부분)되어 형성되는 경우가 있다. 이러한 티타늄 실리사이드의 과도한 응집은 폴리실리콘 내에 존재하는 도펀트를 빼앗기 때문에 콘택 저항을 증가시키고 결국 소자의 전기적 특성을 저하시키는 문제점이 있다.Then, bit lines 17 and 18 having a titanium / titanium nitride / tungsten / antireflection film structure are formed on the entire structure including the contact hole. At this time, the titanium silicide layer (TiSi 2 ; 19) is formed by reacting titanium of the titanium layer 17, which is a lower layer constituting the bit line, with polysilicon of the plug polysilicon layer 15. By the way, this titanium silicide film 19 is not formed uniformly, but may be formed in the bottom of the contact hole for bit line formation by being excessively aggregated (part A). Excessive agglomeration of the titanium silicide has a problem of increasing the contact resistance and eventually deteriorating the electrical characteristics of the device because the dopant existing in the polysilicon is taken away.

따라서, 본 발명은 비트라인용 콘택 홀 형성 후 티타늄을 증착하고 어닐링하므로써 플러그 폴리실리콘 상부에 균일한 분포를 갖도록 티타늄 실리사이드(TiSi2)를 형성하여 폴리실리콘과 티타늄막 간의 확산 방지층으로 사용되도록 하고, 선택적 에치 백(etch back) 공정으로 반응하지 않은 티타늄(Ti)을 제거한 후, 장벽층을 형성하고 비트라인을 형성하므로써, 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 비트라인 형성 방법을 제공하는데 그 목적이 있다.Therefore, the present invention forms titanium silicide (TiSi 2 ) to have a uniform distribution on the top of the plug polysilicon by depositing and annealing the titanium after the formation of the contact hole for the bit line so as to be used as a diffusion barrier layer between the polysilicon and the titanium film. By removing the unreacted titanium (Ti) by the selective etch back process, by forming a barrier layer and a bit line, there is provided a method for forming a bit line of a semiconductor device that can improve the electrical characteristics of the device. The purpose is.

상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 비트라인 형성 방법은 게이트 전극이 형성된 반도체 기판 상에 층간 절연막을 형성한 후 상기 게이트 전극 상부에만 상기 층간 절연막이 잔류하도록 식각 공정을 실시하는 단계와, 전체 구조 상부에 제 1 절연막을 형성한 후 플러그용 콘택 홀을 형성하는 단계와, 전체 구조 상부에 폴리실리콘을 형성한 후 상기 플러그용 콘택 홀 내부에만 상기 폴리실리콘이 매립되도록 에치 백 식각 공정을 실시하여 플러그 폴리실리콘층을 형성하는 단계와, 전체 구조 상부에 티타늄막을 형성한 후 어닐링 공정을 실시하여 상기 플러그 폴리실리콘층 상부의 티타늄막을 티타늄 실리사이드화하고, 상기 어닐링 공정에 의해 반응하지 않은 상기 층간 절연막 상의 티타늄막을 제거하는 단계와, 전체 구조 상부에 제 2 절연막을 형성한 후 비트라인용 콘택 홀을 형성하는 단계와, 전체 구조 상부에 장벽층 및 텅스텐을 순차적으로 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In accordance with an aspect of the present disclosure, a method of forming a bit line of a semiconductor device according to the present invention includes forming an interlayer insulating film on a semiconductor substrate on which a gate electrode is formed, and then performing an etching process such that the interlayer insulating film remains only on the gate electrode. And forming a contact hole for a plug after forming a first insulating film on the entire structure, and forming an polysilicon on the entire structure, and etching the etching back so that the polysilicon is embedded only in the plug contact hole. Forming a plug polysilicon layer, forming a titanium film on the entire structure, and performing an annealing process to titanium silicide the titanium film on the plug polysilicon layer, and not reacting by the annealing process. Removing the titanium film on the interlayer insulating film, and overlying the entire structure Claim characterized in that comprises the steps of forming a barrier layer and a tungsten on the entire upper structure in order to form the contact holes for the bit lines after forming the second insulating film.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2(a) 내지 2(e)는 본 발명에 따른 비트라인 형성 방법을 설명하기 위해 도시한 소자의 단면도이다.2 (a) to 2 (e) are cross-sectional views of the device shown for explaining the bit line forming method according to the present invention.

도 2(a)에 도시된 바와 같이, 소오스(S) 및 드레인(D)이 형성된 반도체 기판(21) 상부에 게이트 전극(22)을 형성한 다음 층간 절연막(23)을 형성한다. 이후, 게이트 전극(22)의 양측부 및 상부에만 층간 절연막(23)이 잔재하도록 식각 공정을 실시한다. 다음에, 전체 구조 상부에 제 1 절연막(24)을 형성하고, 플러그 폴리실리콘 형성을 위한 콘택 홀을 형성한다. 이후, 비소(As), 인(P) 및 비소와 인의 혼합 이온 중 어느 하나를 이용한 이온 주입 공정을 실시하는 것도 가능하다.As shown in FIG. 2A, the gate electrode 22 is formed on the semiconductor substrate 21 on which the source S and the drain D are formed, and then an interlayer insulating layer 23 is formed. Thereafter, an etching process is performed such that the interlayer insulating film 23 remains only on both sides and the upper portion of the gate electrode 22. Next, a first insulating film 24 is formed over the entire structure, and contact holes for forming plug polysilicon are formed. Thereafter, it is also possible to perform an ion implantation process using any one of arsenic (As), phosphorus (P), and mixed ions of arsenic and phosphorus.

도 2(b)에 도시된 바와 같이, 전체 구조 상부에 폴리실리콘을 증착한 후 플러그용 콘택 홀 내부에만 폴리실리콘이 매립되도록 에치 백(etch back) 식각 공정을 실시하여 플러그 폴리실리콘층(25)을 형성한다. 이때, 에치 백 식각 공정은 화학적 기계적 연마(Chemical Mechanical Polishing; CMP) 공정 및 건식 식각 공정 중 어느 하나를 이용하여 실시한다.As shown in FIG. 2 (b), the polysilicon layer is deposited on the entire structure, and then the etch back etching process is performed to bury the polysilicon only in the plug contact hole. To form. In this case, the etch back etching process may be performed using any one of a chemical mechanical polishing (CMP) process and a dry etching process.

이후, 전체 구조 상부에 티타늄막(26)을 형성한다. 여기에서 티타늄막(26)은 이온 메탈 플라즈마(Ion Metal Plasma; IMP), 콜리메이트(collimate) 및 화학기상 증착(Chemical Vapor Deposition; CVD) 방법 중 어느 하나를 이용하여 형성한다.Thereafter, a titanium film 26 is formed on the entire structure. Herein, the titanium film 26 is formed using any one of ion metal plasma (IMP), collimates, and chemical vapor deposition (CVD) methods.

도 2(c)에 도시된 바와 같이, 티타늄막(26)이 형성된 전체 구조에 대하여 어닐링 공정을 실시하여 플러그 폴리실리콘층(25)상부의 티타늄막(26)을 티타늄 실리사이드막(TiSi2; 27)으로 변화시킨다. 이때, 어닐링 공정은 급속 열처리(Rapid Thermal Process; RTP) 어닐링 및 퍼니스(furnace) 어닐링 공정 중 어느 하나를 이용하여 실시한다. 여기에서, RTP 어닐링 공정을 이용할 때에는 500 내지 700℃의 온도에서 10 내지 20초 동안 진행하고, 퍼니스 어닐링 공정을 이용할 때에는 550 내지 700℃의 온도에서 10 내지 30분 동안 진행한다. 이후, 층간 절연막(23) 상부의 반응하지 않은 티타늄은 제거한다. 여기에서 티타늄은 H2SO4 + H2O2 + H2O, NH4OH + H2O2 + H2O 및 NH4F + HF 용액 중 어느 하나를 이용하여 선택적으로 제거한다.As shown in FIG. 2C, an annealing process is performed on the entire structure in which the titanium film 26 is formed, thereby forming a titanium silicide film (TiSi 2 ; 27) on the plug polysilicon layer 25. To). In this case, the annealing process may be performed using any one of a rapid thermal process (RTP) annealing and a furnace annealing process. Here, when using the RTP annealing process is carried out for 10 to 20 seconds at a temperature of 500 to 700 ℃, it is carried out for 10 to 30 minutes at a temperature of 550 to 700 ℃ when using a furnace annealing process. Thereafter, unreacted titanium on the interlayer insulating film 23 is removed. Here titanium is selectively removed using any one of H 2 SO 4 + H 2 O 2 + H 2 O, NH 4 OH + H 2 O 2 + H 2 O and NH 4 F + HF solution.

도 2(d)에 도시된 바와 같이, 전체 구조 상부에 제 2 절연막(28)을 형성한 후 비트라인 형성용 포토레지스트를 이용하여 콘택 홀을 형성한다. 여기에서, 제 2 절연막(28)은 3000 내지 5000Å의 두께로 형성한다.As shown in FIG. 2 (d), the second insulating layer 28 is formed on the entire structure, and then contact holes are formed using a bit line forming photoresist. Here, the second insulating film 28 is formed to a thickness of 3000 to 5000 kPa.

도 2(e)에 도시된 바와 같이, 비트라인용 콘택 홀을 포함한 전체 구조 상부에 장벽층(29)을 형성한다. 이 장벽층(29)은 티타늄/티타늄 나이트라이드 구조를 갖는다. 이때, 티타늄막은 IMP 및 콜리메이트 방법 중 어느 하나의 방법을 이용하여 100 내지 300Å의 두께로 형성하고, 티타늄 나이트라이드막은 CVD, 콜리메이트 및 PVD 방법 중 어느 하나의 방법을 이용하여 100 내지 400Å의 두께로 형성한다. 또한, 티타늄막을 IMP 방법으로 형성할 경우, 고주파(RF) 바이어스는 500watt 인가하여 형성한다. 그리고, 티타늄 나이트라이드막을 CVD 방법으로 형성할 경우, 소오스 물질로는 TDEAT, TDMAT를 사용하며, 증착/플라즈마 처리/증착/플라즈마 처리의 순서로 형성한다. 이와 같은 티타늄 나이트라이드막을 형성하기 위한 플라즈마 처리시에는 소오스 가스로 N2, N2+O2 및 He + O2중 어느 하나를 이용한다. 또한, 티타늄 나이트라이드막을 PVD 방법으로 형성할 경우에는, 증착/대기노출/증착/대기노출의 순서로 형성한다.As shown in FIG. 2 (e), the barrier layer 29 is formed on the entire structure including the contact hole for the bit line. This barrier layer 29 has a titanium / titanium nitride structure. At this time, the titanium film is formed to a thickness of 100 to 300 kPa using any one of the method of IMP and collimation, and the titanium nitride film is 100 to 400 kPa using any one of the method of CVD, collimated and PVD To form. In addition, when the titanium film is formed by the IMP method, a high frequency (RF) bias is formed by applying 500 watts. When the titanium nitride film is formed by the CVD method, TDEAT and TDMAT are used as the source material and are formed in the order of deposition / plasma treatment / deposition / plasma treatment. In the plasma treatment for forming the titanium nitride film, any one of N 2 , N 2 + O 2, and He + O 2 is used as the source gas. In the case where the titanium nitride film is formed by the PVD method, the titanium nitride film is formed in the order of vapor deposition / air exposure / deposition / air exposure.

이후, 전체 구조 상부에 텅스텐(W)을 형성하므로써, 텅스텐-비트라인(30)이 형성된다. 여기에서, 장벽층(29)과 텅스텐-비트라인(30)은 진공파괴 없이 연속적으로 진행하여 형성한다.Then, by forming tungsten (W) over the entire structure, a tungsten-bit line 30 is formed. Here, the barrier layer 29 and the tungsten-bit line 30 are formed to proceed continuously without vacuum destruction.

상술한 바와 같이, 본 발명에 따르면 플러그 폴리실리콘과 비트라인 계면에 형성되는 티타늄 실리사이드막이 균일하게 형성되므로, 콘택 저항을 감소시킬 수 있고 소자의 신호 처리 속도를 개선하여 소자의 특성을 향상시킬 수 있는 탁월한 효과가 있다.As described above, according to the present invention, since the titanium silicide film formed at the interface between the plug polysilicon and the bit line is uniformly formed, the contact resistance can be reduced and the device's signal processing speed can be improved to improve device characteristics. Excellent effect

도 1은 종래 반도체 소자의 비트라인 형성 방법을 설명하기 위해 도시한 소자의 단면도.1 is a cross-sectional view of a device shown for explaining a bit line forming method of a conventional semiconductor device.

도 2(a) 내지 2(e)는 본 발명에 따른 비트라인 형성 방법을 설명하기 위해 도시한 소자의 단면도.2 (a) to 2 (e) are cross-sectional views of the device shown for explaining the bit line forming method according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

21 : 반도체 기판 22 : 게이트 전극21 semiconductor substrate 22 gate electrode

23 : 층간 절연막 24 : 제 1 절연막23: interlayer insulating film 24: first insulating film

25 : 플러그 폴리실리콘층 26 : 티타늄막25 plug polysilicon layer 26 titanium film

27 : 티타늄 실리사이드막 28 : 제 2 절연막27: titanium silicide film 28: second insulating film

29 : 장벽층 30 : 비트라인29 barrier layer 30 bit line

Claims (6)

게이트 전극이 형성된 반도체 기판 상에 층간 절연막을 형성한 후 상기 게이트 전극 상부에만 상기 층간 절연막이 잔류하도록 식각공정을 실시하는 단계와,Forming an interlayer insulating film on the semiconductor substrate on which the gate electrode is formed, and then performing an etching process such that the interlayer insulating film remains only on the gate electrode; 전체 구조 상부에 제 1 절연막을 형성한 후 플러그용 콘택 홀을 형성하는 단계와,Forming a plug contact hole after the first insulating film is formed over the entire structure; 전체 구조 상부에 폴리실리콘을 형성한 후 상기 플러그용 콘택 홀 내부에만 상기 폴리실리콘이 매립되도록 에치 백 식각 공정을 실시하여 플러그 폴리실리콘층을 형성하는 단계와,Forming a polysilicon layer on the entire structure and then performing an etch back etching process so that the polysilicon is embedded only in the plug contact hole; 전체 구조 상부에 티타늄막을 형성한 후 어닐링 공정을 실시하여 상기 플러그 폴리실리콘층 상부의 티타늄막을 티타늄 실리사이드화하고, 상기 어닐링 공정에 의해 반응하지 않은 상기 층간 절연막 상의 티타늄막을 제거하는 단계와,Forming a titanium film on the entire structure and then performing an annealing process to titanium silicide the titanium film on the plug polysilicon layer, and removing the titanium film on the interlayer insulating film not reacted by the annealing process; 전체 구조 상부에 제 2 절연막을 형성한 후 비트라인용 콘택 홀을 형성하는 단계와,Forming a bit line contact hole after forming a second insulating film over the entire structure; 전체 구조 상부에 장벽층 및 텅스텐을 순차적으로 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 비트라인 형성 방법.And sequentially forming a barrier layer and tungsten on the entire structure. 제 1 항에 있어서 상기 티타늄막은 이온 메탈 플라즈마, 콜리메이트 및 화학기상 증착 방법 중 어느 하나를 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 비트라인 형성 방법.The method of claim 1, wherein the titanium film is formed using any one of an ion metal plasma, a collimate method, and a chemical vapor deposition method. 제 1 항에 있어서,The method of claim 1, 상기 어닐링 공정은 급속 열처리 어닐링 및 퍼니스 어닐링 공정 중 어느 하나를 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 비트라인 형성 방법.And the annealing process is performed using any one of a rapid heat treatment annealing process and a furnace annealing process. 제 3 항에 있어서,The method of claim 3, wherein 상기 급속 열처리 어닐링 공정은 500 내지 700℃의 온도에서 10 내지 20초 동안 진행하고, 상기 퍼니스 어닐링 공정은 550 내지 700℃의 온도에서 10 내지 30분 동안 진행하는 것을 특징으로 하는 반도체 소자의 비트라인 형성 방법.The rapid thermal annealing process is performed for 10 to 20 seconds at a temperature of 500 to 700 ℃, the furnace annealing process is performed for 10 to 30 minutes at a temperature of 550 to 700 ℃ bit line formation of the semiconductor device Way. 제 1 항에 있어서,The method of claim 1, 상기 층간 절연막 상부의 반응하지 않은 티타늄은 H2SO4 + H2O2 + H2O, NH4OH + H2O2 + H2O 및 NH4F + HF 용액 중 어느 하나를 이용하여 선택적으로 제거하는 것을 특징으로 하는 반도체 소자의 비트라인 형성 방법.The unreacted titanium on the interlayer insulating film is selectively selected using any one of H 2 SO 4 + H 2 O 2 + H 2 O, NH 4 OH + H 2 O 2 + H 2 O and NH 4 F + HF solution. And forming a bit line of the semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 장벽층은 티타늄/티타늄 나이트라이드 구조로 형성하는 것을 특징으로 하는 반도체 소자의 비트라인 형성 방법.And the barrier layer is formed of a titanium / titanium nitride structure.
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JPH0215620A (en) * 1988-07-01 1990-01-19 Nec Corp Manufacture of semiconductor device
JPH04290425A (en) * 1991-03-19 1992-10-15 Sony Corp Formation of heat-resisting wiring
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JPH0215620A (en) * 1988-07-01 1990-01-19 Nec Corp Manufacture of semiconductor device
JPH04290425A (en) * 1991-03-19 1992-10-15 Sony Corp Formation of heat-resisting wiring
KR960002682A (en) * 1994-06-30 1996-01-26 김주용 Metal wiring formation method of semiconductor device

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