JPH04290425A - Formation of heat-resisting wiring - Google Patents
Formation of heat-resisting wiringInfo
- Publication number
- JPH04290425A JPH04290425A JP5502891A JP5502891A JPH04290425A JP H04290425 A JPH04290425 A JP H04290425A JP 5502891 A JP5502891 A JP 5502891A JP 5502891 A JP5502891 A JP 5502891A JP H04290425 A JPH04290425 A JP H04290425A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- contact hole
- wiring
- forming
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000002844 melting Methods 0.000 claims abstract description 7
- 230000008018 melting Effects 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 24
- 229910052721 tungsten Inorganic materials 0.000 abstract description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 7
- 239000010937 tungsten Substances 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910008479 TiSi2 Inorganic materials 0.000 description 8
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910003074 TiCl4 Inorganic materials 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910010348 TiF3 Inorganic materials 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、耐熱性配線の形成方法
に係り、特に超ＬＳＩ等のように高集積化を図るために
必要な電気抵抗が低い耐熱性配線の形成方法に関するも
のである。[Field of Industrial Application] The present invention relates to a method for forming heat-resistant wiring, and more particularly to a method for forming heat-resistant wiring with low electrical resistance, which is necessary for achieving high integration such as in ultra-LSIs. .
【０００２】0002
【従来の技術】サブミクロン以下の寸法の微細化が設計
上必要とされる超ＬＳＩでは、第１層の配線よりも上層
に負荷トランジスタ（Ｔｒ）等を形成することが考えら
れている。このために第１層の配線およびこの配線とそ
の近傍の拡散層とのコンタクトが、少なくともＴｒ形成
のプロセスに耐える耐熱性（例えば９００℃以上）を有
し、しかも電気抵抗が低いことを要する。2. Description of the Related Art In ultra-LSIs whose design requires miniaturization of submicron dimensions or less, it has been considered to form load transistors (Tr) and the like in a layer above the first layer wiring. For this purpose, it is necessary that the first layer wiring and the contact between the wiring and the diffusion layer in the vicinity have heat resistance (for example, 900° C. or higher) that can at least withstand the process of forming the Tr, and have low electrical resistance.
【０００３】0003
【発明が解決しようとする課題】９００℃以上の耐熱性
を有し、電気抵抗が低い配線としては、高融点金属、特
にタングステン（Ｗ）を用いた配線が注目される。しか
し、ＬＳＩプロセスではＷを例えば拡散層のシリコン（
Ｓｉ）に直接被着させると、６００℃以上の熱処理によ
りシリサイド化（ＷＳｉ２）反応を生じ耐熱性コンタク
トが得られない。そこで、Ｗと拡散層との間に窒化チタ
ン（ＴｉＮ）等のバリアメタル層を形成して、ＷとＳｉ
のシリサイド化を防止する方法が考えられている。Problems to be Solved by the Invention As wiring having heat resistance of 900° C. or higher and low electrical resistance, wiring using a high melting point metal, particularly tungsten (W), is attracting attention. However, in the LSI process, W is used, for example, in the silicon of the diffusion layer (
If it is directly deposited on Si), a silicidation (WSi2) reaction occurs due to heat treatment at 600° C. or higher, making it impossible to obtain a heat-resistant contact. Therefore, a barrier metal layer such as titanium nitride (TiN) is formed between W and the diffusion layer to
Methods are being considered to prevent silicide formation.
【０００４】しかしながら、ＴｉＮをＷとＳｉ層に介在
させる方法も以下の如き問題があった。However, the method of interposing TiN between the W and Si layers also has the following problems.
【０００５】第１の問題は、バリアメタルとしてのＴｉ
Ｎは、通常スパッタ法で形成されるために、Ｗ配線用コ
ンタクトホール開口の径が微細化し、なおかつその深さ
が深くなると、図４（ａ）に示すように、ＴｉＮ１４が
Ｓｉ基板１１上のＳｉＯ２層間絶縁膜１２のコンタクト
ホール１３下部では薄く被着し、上部ではオーバーハン
グ（上方になるにしたがって開口部が狭くなる）が生じ
るので、その後の全面Ｗ１５被着がＴｉＮ１４の被着形
成状態により図４（ｂ）に示すようにコンタクトホール
底部でボイド等の空隙部１６を形成することがある。The first problem is that Ti as a barrier metal
Since N is usually formed by a sputtering method, as the diameter of the contact hole opening for W wiring becomes finer and its depth becomes deeper, TiN 14 is formed on the Si substrate 11 as shown in FIG. 4(a). The SiO2 interlayer insulating film 12 is thinly deposited at the bottom of the contact hole 13, and an overhang occurs at the top (the opening becomes narrower as it goes upward). As shown in FIG. 4(b), a void 16 such as a void may be formed at the bottom of the contact hole.
【０００６】第２の問題は、ＴｉＮは上記スパッタ法の
他、ＣＶＤ（化学気相成長）法で形成するプロセスが知
られている。しかし、まだ開発の段階であり、例えば塩
素（Ｃｌ）等の不純物をＴｉＮ内に取り込み、要求され
るバリア性を低下させることである。[0006] The second problem is that, in addition to the above-mentioned sputtering method, a process for forming TiN using a CVD (chemical vapor deposition) method is known. However, it is still in the development stage, and the challenge is to introduce impurities, such as chlorine (Cl), into TiN and reduce the required barrier properties.
【０００７】本発明は、タングステン（Ｗ）等の高融点
金属と、Ｓｉとのシリサイド化を防止するためコンタク
トホール内にバリア層を容易に形成しうる耐熱性配線の
形成方法を提供することを目的とする。An object of the present invention is to provide a method for forming a heat-resistant wiring that can easily form a barrier layer in a contact hole to prevent silicidation between a high-melting point metal such as tungsten (W) and Si. purpose.
【０００８】[0008]
【課題を解決するための手段】上記課題は本発明によれ
ば、シリコン基板上に絶縁層を形成し、前記シリコン基
板表面を露出させるコンタクトホールを前記絶縁層に形
成し、前記コンタクトホール内に前記シリコン基板とコ
ンタクトするチタンシリサイド埋込み層を選択的に形成
し、バリア層および密着層としての窒化チタン層を全面
に形成した後、高融点金属層を全面に形成して前記チタ
ンシリサイド埋込み層とコンタクトする配線を形成する
ことを特徴とする耐熱性配線の形成方法によって解決さ
れる。[Means for Solving the Problems] According to the present invention, an insulating layer is formed on a silicon substrate, a contact hole exposing the surface of the silicon substrate is formed in the insulating layer, and a contact hole is formed in the contact hole. After selectively forming a titanium silicide buried layer in contact with the silicon substrate, and forming a titanium nitride layer as a barrier layer and an adhesion layer on the entire surface, a high melting point metal layer is formed on the entire surface to connect with the titanium silicide buried layer. The problem is solved by a method for forming heat-resistant wiring, which is characterized by forming contact wiring.
【０００９】更に、上記課題は本発明によれば、上記方
法におけるチタンシリサイド埋込み層を形成した後、該
チタンシリサイド埋込み層上にのみ自己整合的にバリア
層としての窒化チタン層を予め形成することによっても
解決される。Furthermore, according to the present invention, the above problem is solved by forming a titanium nitride layer as a barrier layer in advance in a self-aligned manner only on the titanium silicide buried layer after forming the titanium silicide buried layer in the above method. It is also solved by
【００１０】本発明では、コンタクトホールは開口幅が
サブミクロンの微細な場合で特に開口径より深さが大き
な（アスペクト比が大）場合に有効である。また、本発
明ではチタンシリサイド埋込み層の厚さがコンタクトホ
ール深さの１／２以上であればアスペクト比を小にする
上で好ましい。本発明では、高融点金属としてタングス
テン、モリブデン等が好ましく用いられる。また本発明
ではチタンシリサイド埋込み層上にのみ自己整合的にバ
リア層として窒化チタン層を形成する方法として、ＮＨ
３等の窒素雰囲気中でＴｉＳｉ２を熱処理することによ
り容易に得られる。[0010] The present invention is effective when the contact hole has a submicron opening width and is particularly effective when the depth is larger than the opening diameter (large aspect ratio). Further, in the present invention, it is preferable that the thickness of the titanium silicide buried layer is 1/2 or more of the contact hole depth in order to reduce the aspect ratio. In the present invention, tungsten, molybdenum, etc. are preferably used as the high melting point metal. In addition, in the present invention, as a method for forming a titanium nitride layer as a barrier layer only on a titanium silicide buried layer in a self-aligned manner, NH
It can be easily obtained by heat treating TiSi2 in a nitrogen atmosphere such as No. 3.
【００１１】[0011]
【作用】本発明によれば、アスペクト比が大きなコンタ
クトホール内に予めチタンシリサイドを埋込みアスペク
ト比を小にしているため、バリア層、密着層としてのＴ
ｉＮ膜を良好に、しかも容易に形成できる。そのため、
耐熱性配線も確実に形成される。[Operation] According to the present invention, since titanium silicide is buried in advance in a contact hole with a large aspect ratio to reduce the aspect ratio, T.
An iN film can be formed easily and favorably. Therefore,
Heat-resistant wiring can also be reliably formed.
【００１２】0012
【実施例】以下、本発明の実施例を図面に基づいて説明
する。Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings.
【００１３】図１および図２は本発明の第１実施例を示
す工程断面図であり、特に図１は前半の工程、図２は後
半の工程を示す。FIGS. 1 and 2 are process cross-sectional views showing a first embodiment of the present invention. In particular, FIG. 1 shows the first half of the process, and FIG. 2 shows the second half of the process.
【００１４】まず、図１（ａ）に示すように、Ｓｉ基板
１上の、例えば層間絶縁膜である厚さ８０００オングス
トロームのＳｉＯ２膜２に径０．４μｍのコンタクトホ
ール３を形成した後、ＳｉＨ４とＴｉＣｌ４を反応ガス
としてＴｉＳｉ２をコンタクトホール内に約６４００オ
ングストローム（コンタクトホール深さの８０％）の厚
さに選択的に埋込み、ＴｉＳｉ２埋込み層４を形成する
。First, as shown in FIG. 1(a), a contact hole 3 with a diameter of 0.4 μm is formed in a SiO2 film 2 with a thickness of 8000 angstroms, which is an interlayer insulating film, for example, on a Si substrate 1, and then SiH4 A TiSi2 buried layer 4 is formed by selectively burying TiSi2 into the contact hole to a thickness of about 6400 angstroms (80% of the contact hole depth) using and TiCl4 as a reactive gas.
【００１５】ＴｉＳｉ２埋込み層４の成長条件は、反応
ガスＴｉＣｌ４とＳｉＨ４の流量をそれぞれ０．１５Ｓ
ＣＣＭ、５０ＳＣＣＭとし、成長温度を７２０〜７４０
℃、圧力を１×１０−３〜５×１０−５Ｔｏｒｒとした
。The growth conditions for the TiSi2 buried layer 4 are such that the flow rates of the reactive gases TiCl4 and SiH4 are each 0.15S.
CCM, 50SCCM, growth temperature 720-740
℃ and the pressure was 1×10 −3 to 5×10 −5 Torr.
【００１６】次に、図１（ｂ）に示すように、ＮＨ３雰
囲気中でＴｉＳｉ２埋込み層４をアニールし、その表面
を窒化し、厚さ約３００オングストロームのＴｉＮ膜５
を形成する。アニール条件は熱処理温度を７００〜１０
００℃で２０秒間行なった。Next, as shown in FIG. 1(b), the TiSi2 buried layer 4 is annealed in an NH3 atmosphere, its surface is nitrided, and a TiN film 5 with a thickness of approximately 300 angstroms is formed.
form. Annealing conditions include heat treatment temperature of 700 to 10
The test was carried out at 00°C for 20 seconds.
【００１７】次に、図１（ｃ）に示すように、ブランケ
ットタングステン（全面被着Ｗ）の密着層としてスパッ
タ法を用いてスパッタＴｉＮを堆積し、厚さ約１０００
オングストロームスパッタＴｉＮ膜６を形成する。この
スパッタＴｉＮ膜６の形成ではコンタクトホール３が予
めＴｉＳｉ２で埋め込まれ浅くなっているため、いわゆ
るアスペクト比が小となり、従来問題であったＴｉＮの
オーバーハングも緩和され、図２で示す後工程の配線形
成にも悪影響を及ぼさない。Next, as shown in FIG. 1(c), sputtered TiN was deposited using a sputtering method as an adhesion layer for blanket tungsten (W coated on the entire surface) to a thickness of approximately 1000 mm.
An angstrom sputtered TiN film 6 is formed. In the formation of this sputtered TiN film 6, the contact hole 3 is filled with TiSi2 in advance and becomes shallow, so the so-called aspect ratio becomes small, and the overhang of TiN, which was a conventional problem, is alleviated, and the post-process shown in FIG. It does not adversely affect wiring formation.
【００１８】すなわち、スパッタＴｉＮ膜６を形成後、
図２（ａ）で示すように、コンタクトホールを埋め込む
ように全面にタングステン（Ｗ）をＣＶＤ法により被着
してＷ層７を形成する。このＷ層７のＣＶＤ条件は４０
０℃の温度、３０Ｔｏｒｒの気圧及びキャリアガスＨ２
と原料ガスＷＦ６の流量比（Ｈ２／ＷＦ６）を１７．０
とした。That is, after forming the sputtered TiN film 6,
As shown in FIG. 2A, a W layer 7 is formed by depositing tungsten (W) on the entire surface by CVD so as to fill the contact hole. The CVD conditions for this W layer 7 are 40
Temperature of 0°C, pressure of 30 Torr and carrier gas H2
and the flow rate ratio of raw material gas WF6 (H2/WF6) to 17.0.
And so.
【００１９】次に、図２（ｂ）に示すように、図２（ａ
）の状態からエッチバックによりＷ層７およびスパッタ
ＴｉＮ層６を順次除去することによって、Ｗ埋込み配線
８が得られる。Ｗ層７のエッチバックの際のエッチング
では、ＳＦ６とＯ２（２０％）の混合ガスを用いたＲＩ
Ｅ（反応性イオンエッチング）を使用した。一方、スパ
ッタＴｉＮ膜６のエッチバックの際のエッチングではＣ
ｌ２ガスを用いたＲＩＥを使用した。また、Ｗ層７をエ
ッチバックせずに、そのまま配線として用いてもよい。Next, as shown in FIG. 2(b), FIG.
), by sequentially removing the W layer 7 and the sputtered TiN layer 6 by etching back, the W buried wiring 8 is obtained. During the etch-back of the W layer 7, RI using a mixed gas of SF6 and O2 (20%) was performed.
E (reactive ion etching) was used. On the other hand, during etching back of the sputtered TiN film 6, C
RIE with l2 gas was used. Further, the W layer 7 may be used as a wiring without being etched back.
【００２０】図３は本発明の第２実施例を示す工程断面
図であり、図から明らかなように、図１，２で示した第
１実施例において、ＴｉＳｉ２埋込み層４とスパッタＴ
ｉＮ膜６間の薄いＴｉＮ膜５が形成されていない実施例
である。すなわち、図１（ａ）の状態から直接図１（ｃ
）以下で説明したと同様にスパッタＴｉＮ膜６を形成（
図３（ａ））し、Ｗ層７をＣＶＤ法で形成し（図３（ｂ
））、更にＷ層７をエッチバックすることによってＷ埋
込み配線８が得られた。また、Ｗ層７をエッチバックせ
ずに、そのまま配線として用いてもよい。FIG. 3 is a process sectional view showing a second embodiment of the present invention. As is clear from the figure, in the first embodiment shown in FIGS. 1 and 2, the TiSi2 buried layer 4 and the sputtered T
This is an example in which the thin TiN film 5 between the iN films 6 is not formed. In other words, directly from the state of FIG. 1(a) to FIG. 1(c)
) A sputtered TiN film 6 is formed in the same manner as explained below (
3(a)), and a W layer 7 is formed by CVD method (FIG. 3(b)).
)), and by further etching back the W layer 7, a W buried wiring 8 was obtained. Further, the W layer 7 may be used as a wiring without being etched back.
【００２１】[0021]
【発明の効果】以上説明したように、この発明によれば
コンタクトホール底部にＴｉＮ／ＴｉＳｉ２構造を得て
コンタクトホールを予め浅くすることによって、アスペ
クト比を小にし、ブランケットタングステン（全面被着
Ｗ）の密着層バリア層であるスパッタＴｉＮのオーバー
ハングを防止できると共に、例えばＷ配線ではチタンシ
リサイドと原料ＷＦ６とが直接接触されないため絶縁物
ＴｉＦ３が形成されず低コンタクト抵抗も実現できる。As explained above, according to the present invention, the TiN/TiSi2 structure is obtained at the bottom of the contact hole and the contact hole is made shallow in advance, thereby reducing the aspect ratio and reducing the blanket tungsten (full surface deposition). Overhang of sputtered TiN, which is the adhesion layer barrier layer, can be prevented, and, for example, in W wiring, the titanium silicide and the raw material WF6 are not in direct contact, so the insulator TiF3 is not formed, and low contact resistance can be achieved.
【図１】本発明の方法の第１実施例における前半の工程
断面図である。FIG. 1 is a sectional view of the first half of the process in a first embodiment of the method of the present invention.
【図２】本発明の方法の第１実施例における後半の工程
断面図である。FIG. 2 is a sectional view of the second half of the process in the first embodiment of the method of the present invention.
【図３】本発明の第２実施例を示す工程断面図である。FIG. 3 is a process sectional view showing a second embodiment of the present invention.
【図４】従来の技術を説明するための工程断面図である
。FIG. 4 is a process sectional view for explaining a conventional technique.
１，１１ Ｓｉ基板 ２ ＳｉＯ２膜 ３，１３ コンタクトホール ４ ＴｉＳｉ２埋込み層 ５ ＴｉＮ膜 ６ スパッタＴｉＮ膜 ７ Ｗ層 ８ Ｗ埋め込み配線 １２ ＳｉＯ２層間絶縁膜 １４ ＴｉＮ １５ Ｗ １６ 空隙部 1,11 Si substrate 2 SiO2 film 3,13 Contact hole 4 TiSi2 buried layer 5 TiN film 6 Sputtered TiN film 7 W layer 8 W embedded wiring 12 SiO2 interlayer insulation film 14 TiN 15 W 16 Void part
Claims (2)
記シリコン基板表面を露出させるコンタクトホールを前
記絶縁層に形成し、前記コンタクトホール内に前記シリ
コン基板とコンタクトするチタンシリサイド埋込み層を
選択的に形成し、バリア層および密着層としての窒化チ
タン層を全面に形成した後、高融点金属層を全面に形成
して前記チタンシリサイド埋込み層とコンタクトする配
線を形成することを特徴とする耐熱性配線の形成方法。1. An insulating layer is formed on a silicon substrate, a contact hole is formed in the insulating layer to expose a surface of the silicon substrate, and a titanium silicide buried layer is selectively provided in the contact hole in contact with the silicon substrate. After forming a titanium nitride layer as a barrier layer and an adhesion layer on the entire surface, a high melting point metal layer is formed on the entire surface to form wiring in contact with the titanium silicide buried layer. How to form wiring.
した後、該チタンシリサイド埋込み層上にのみ自己整合
的にバリア層としての窒化チタン層を予め形成すること
を特徴とする請求項１記載の方法。2. The method according to claim 1, wherein after forming the titanium silicide buried layer, a titanium nitride layer as a barrier layer is previously formed in a self-aligned manner only on the titanium silicide buried layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5502891A JPH04290425A (en) | 1991-03-19 | 1991-03-19 | Formation of heat-resisting wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5502891A JPH04290425A (en) | 1991-03-19 | 1991-03-19 | Formation of heat-resisting wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04290425A true JPH04290425A (en) | 1992-10-15 |
Family
ID=12987217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5502891A Pending JPH04290425A (en) | 1991-03-19 | 1991-03-19 | Formation of heat-resisting wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04290425A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100486874B1 (en) * | 1998-06-30 | 2005-08-01 | 주식회사 하이닉스반도체 | Bit line formation method of semiconductor device |
-
1991
- 1991-03-19 JP JP5502891A patent/JPH04290425A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100486874B1 (en) * | 1998-06-30 | 2005-08-01 | 주식회사 하이닉스반도체 | Bit line formation method of semiconductor device |
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