KR100401147B1 - Substrate for manufacturing semiconductor package and method for manufacturing semiconductor package using the same - Google Patents

Substrate for manufacturing semiconductor package and method for manufacturing semiconductor package using the same Download PDF

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KR100401147B1
KR100401147B1 KR10-2001-0000241A KR20010000241A KR100401147B1 KR 100401147 B1 KR100401147 B1 KR 100401147B1 KR 20010000241 A KR20010000241 A KR 20010000241A KR 100401147 B1 KR100401147 B1 KR 100401147B1
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South Korea
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semiconductor package
region
molding
regions
attaching
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KR10-2001-0000241A
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Korean (ko)
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KR20020059176A (en
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아키토요시다
신원선
이춘흥
이선구
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앰코 테크놀로지 코리아 주식회사
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Priority to KR10-2001-0000241A priority Critical patent/KR100401147B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 반도체 패키지 제조용 부재와 이것을 이용한 반도체 패키지 제조방법에 관한 것으로서, 다수의 반도체 패키지 영역이 매트릭스 배열로 형성하되 부재의 각 반도체 패키지 영역의양쪽에 인출단자 부착용 랜드를 배열시키는 동시에 랜드의 안쪽 영역을 몰딩영역으로 형성한 반도체 패키지 제조용 부재와, 이렇게 구성된 다수의 반도체 패키지 영역중 일렬을 하나의 그룹으로 설정하여, 이 그룹으로 설정된 반도체 패키지 영역내의 몰딩영역을 한꺼번에 몰딩할 수 있도록 함으로써, 다수의 반도체 패키지 영역을 조밀하게 유지하는 동시에 반도체 패키지로 제조후 적층이 가능하도록 한 반도체 패키지 제조방법을 제공하고자 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package manufacturing member and a method for manufacturing a semiconductor package using the same, wherein a plurality of semiconductor package regions are formed in a matrix arrangement, and lands for attaching the extraction terminal are arranged on both sides of each semiconductor package region of the member, and at the same time the inner region of the land And a plurality of semiconductors by forming a semiconductor package manufacturing member formed of a molding region and a plurality of semiconductor package regions constituted as one group so that molding regions in the semiconductor package region set in this group can be molded at once. An object of the present invention is to provide a method of manufacturing a semiconductor package, which allows the package area to be densely maintained while being laminated with a semiconductor package.

Description

반도체 패키지 제조용 부재와 이것을 이용한 반도체 패키지 제조방법{Substrate for manufacturing semiconductor package and method for manufacturing semiconductor package using the same}Substrate for manufacturing semiconductor package and method for manufacturing semiconductor package using the same}

본 발명은 반도체 패키지 제조용 부재와 이것을 이용한 반도체 패키지 제조방법에 관한 것으로서, 더욱 상세하게는 다수의 반도체 패키지 영역이 매트릭스 배열로 형성된 반도체 패키지 제조용 부재와, 이 부재에서 가로 및 세로 방향으로 배열된 다수의 반도체 패키지 영역중 일렬을 하나의 그룹으로 설정하여, 이 그룹으로 설정된 반도체 패키지 영역내의 몰딩영역을 한꺼번에 몰딩할 수 있도록 한 반도체 패키지 제조방법에 관한 것이다.The present invention relates to a semiconductor package manufacturing member and a semiconductor package manufacturing method using the same, and more particularly, a semiconductor package manufacturing member in which a plurality of semiconductor package regions are formed in a matrix arrangement, The present invention relates to a method for manufacturing a semiconductor package in which a row of semiconductor package regions is set to one group so that molding regions in the semiconductor package region set in this group can be molded at once.

통상적으로 반도체 패키지는 리드프레임, 인쇄회로기판, 회로필름등과 같은 각종 부재를 이용하여 다양한 구조로 제조되고 있는 바, 최근에는 칩 스케일 패키지(CSP:Chip Scale Package)라 하여, 반도체 패키지가 칩의 크기에 가깝게 경박단소화로 제조되는 추세에 있다.In general, semiconductor packages are manufactured in various structures using various members such as lead frames, printed circuit boards, and circuit films. Recently, semiconductor packages are referred to as chip scale packages (CSPs). There is a tendency to make it light and small in size.

대개, 상기 칩 스케일의 반도체 패키지를 제조하기 위한 인쇄회로기판 부재에는 반도체 패키지 영역이 설계에 따라 3×4, 4×4 등의 매트릭스 배열을 이루며 조밀하게 형성되어 있다.Usually, the semiconductor package region is densely formed in a matrix arrangement of 3x4, 4x4, etc. according to the design in the printed circuit board member for manufacturing the chip scale semiconductor package.

여기서, 상기 반도체 패키지 제조용 부재를 사용하여 칩 스케일 패키지의 일종인 칩 어레이 타입의 반도체 패키지의 제조 방법을 간략히 설명하면 다음과 같다.Here, a method of manufacturing a chip array type semiconductor package, which is a type of chip scale package using the semiconductor package manufacturing member, will be briefly described as follows.

상기 부재(10b)는 인쇄회로기판으로서, 도 5에 도시한 바와 같이 베이스층인 수지층(22)과; 이 수지층상에 식각 처리된 전도성패턴(24)과; 이 전도성패턴(24)들중 인출단자 부착용 전도성패턴과 와이어 본딩용 전도성패턴을 상부로 노출시키면서 상기 수지층(22)상에 도포된 커버코트(26)로 구성되어 있다.The member 10b is a printed circuit board, and a resin layer 22 serving as a base layer as shown in FIG. 5; A conductive pattern 24 etched on the resin layer; The conductive pattern 24 is composed of a cover coat 26 applied on the resin layer 22 while exposing the conductive pattern for attaching the lead terminal and the conductive pattern for wire bonding to the top.

따라서, 상기 부재(10b)상에 매트릭스 배열을 이루고 있는 각 반도체 패키지 영역의 칩탑재영역에 반도체 칩(28)을 접착수단(30)으로 부착하는 단계와; 상기 반도체 칩(28)의 본딩패드와 부재(10b)의 와이어 본딩용 전도성패턴간을 와이어(32)로 본딩하는 단계와; 상기 반도체 칩(28)과 와이어(32)등을 포함하는 각 반도체 패키지의 몰딩영역을 한꺼번에 수지(34)로 몰딩하는 단계와; 상기 인출단자 부착용 전도성패턴에 전도성의 솔더볼(36)을 부착하는 단계와; 상기 각각의 반도체 패키지 영역을 블레이드와 같은 소잉수단을 사용하여 낱개의 반도체 패키지로 싱귤레이션하는 단계등을 거쳐, 첨부한 도 5에 도시한 바와 같은 구조의 반도체 패키지(200)로 제조되어진다.Therefore, the step of attaching the semiconductor chip 28 to the chip mounting region of each semiconductor package region in the matrix arrangement on the member 10b with the bonding means 30; Bonding between the bonding pad of the semiconductor chip 28 and the conductive pattern for wire bonding of the member 10b with a wire 32; Molding a molding region of each semiconductor package including the semiconductor chip 28, the wire 32, and the like with resin 34 at one time; Attaching a conductive solder ball 36 to the conductive terminal attachment pattern; Each semiconductor package region is manufactured into a semiconductor package 200 having a structure as shown in FIG.

보다 상세하게는 상기 몰딩공정에 있어서, 첨부한 도 4에 도시한 바와 같이 인쇄회로기판 부재(10b)상의 매트릭스 배열로 이루어진 각각의 반도체 패키지 영역(12)이 한꺼번에 수지(34)로 몰딩되고, 상기 반도체 패키지 영역(12) 라인(=싱귤레이션 라인)을 따라 블레이드와 같은 소잉수단으로 소잉을 함으로써, 낱개의 반도체 패키지로 싱귤레이션되어진다.More specifically, in the molding process, as shown in the accompanying FIG. 4, each semiconductor package region 12 having a matrix arrangement on the printed circuit board member 10b is molded at one time with the resin 34, and By sawing by sawing means such as a blade along the semiconductor package region 12 line (= singulation line), it is singulated into a single semiconductor package.

그러나, 상기와 같은 칩 스케일 반도체 패키지 제조용 부재는 다음과 같은 단점이 있다.However, such a chip scale semiconductor package manufacturing member has the following disadvantages.

즉, 부재내에 다수의 반도체 패키지 영역을 최대로 수용하여, 다수의 반도체 패키지를 동시에 생산할 수 있는 점에서 유용하나, 일면 전체가 수지로 몰딩된 상태이기 때문에, 반도체 패키지를 적층하여 구성할 수 없는 단점이 있다.That is, it is useful in that it can accommodate a large number of semiconductor package regions in a member to produce a large number of semiconductor packages at the same time. However, since the whole surface is molded with resin, the semiconductor packages cannot be laminated. There is this.

여기서, 칩 스케일 패키지의 또 다른 일종으로서, 다수의 반도체 패키지 영역(12)이 타이바(38)에 의하여 연결되며 매트릭스 배열을 이루고 있는 인쇄회로기판 부재(10c)를 이용하여 제조된 또 다른 형태의 칩 스케일 패키지에 대하여 첨부한 도 6내지 도 7을 참조로 설명하면 다음과 같다.Here, as another kind of chip scale package, a plurality of semiconductor package regions 12 are connected by tie bars 38 and formed of another type of printed circuit board member 10c in a matrix arrangement. The chip scale package is described with reference to FIGS. 6 to 7 as follows.

상기 인쇄회로기판 부재(10c)는 도 6에 도시한 바와 같이, 4 ×4, 4 ×5등의 매트릭스 배열로 된 다수의 반도체 패키지 영역(12)이 서로 타이바(38)에 의하여 연결되어 있고, 수지층(22)의 상하면에 전도성패턴(24)이 식각처리되어 있으며, 와이어 본딩 및 인출단자 부착용 전도성패턴을 외부로 노출시키면서 수지층(22)상에 커버코트(26)가 도포되어 있다.As shown in FIG. 6, the printed circuit board member 10c includes a plurality of semiconductor package regions 12 having a matrix arrangement such as 4 × 4 and 4 × 5, which are connected to each other by tie bars 38. The conductive pattern 24 is etched on the upper and lower surfaces of the resin layer 22, and the cover coat 26 is coated on the resin layer 22 while exposing the conductive pattern for wire bonding and the extraction terminal to the outside.

각 반도체 패키지 영역(12)에는 칩 부착용 홀(40)이 형성되어 있고, 상기홀(40)을 마감시키기 위하여 부재(10c)의 일면에는 접착테이프가 부착되어 있다.A chip attaching hole 40 is formed in each semiconductor package region 12, and an adhesive tape is attached to one surface of the member 10c to close the hole 40.

따라서, 상기 인쇄회로기판 부재(10c)의 칩 부착용 홀(40)에 반도체 칩(28)을 픽업하여 접착테이프에 부착시키는 단계와; 상기 반도체 칩(28)의 본딩패드와 상기 인쇄회로기판 부재(10c)의 와이어 본딩용 전도성패턴간을 와이어(32)로 본딩하는 단계와; 상기 홀(40)내에 위치된 반도체 칩(28)과, 와이어(32)와, 와이어 본딩용 전도성패턴등을 수지(34)로 몰딩하는 단계와; 인쇄회로기판 부재(10c)의 인출단자 부착용 전도성패턴에 전도성의 솔더볼(36)를 부착하는 단계와; 상기 반도체 칩(28)의 저면이 외부로 노출되도록 상기 부재(10c) 저면의 접착테이프를 떼어내는 단계와; 상기 각 반도체 패키지 영역(12)을 연결하고 있는 타이바(38)를 펀칭으로 제거해주어 낱개의 반도체 패키지로 분리하는 단계등을 거쳐 첨부한 도 7에 도시한 바와 같은 칩 스케일의 반도체 패키지(300)로 제조된다.Therefore, the step of picking up the semiconductor chip 28 in the chip attaching hole 40 of the printed circuit board member 10c and attaching it to the adhesive tape; Bonding between the bonding pad of the semiconductor chip 28 and the conductive pattern for wire bonding of the printed circuit board member 10c with a wire 32; Molding a semiconductor chip (28), a wire (32), a conductive pattern for wire bonding, etc., located in the hole (40) with a resin (34); Attaching a conductive solder ball 36 to a conductive pattern for attaching a lead terminal of the printed circuit board member 10c; Removing the adhesive tape on the bottom surface of the member (10c) so that the bottom surface of the semiconductor chip (28) is exposed to the outside; A chip-scale semiconductor package 300 as shown in FIG. 7 is attached through a step of removing the tie bars 38 connecting the semiconductor package regions 12 by punching to separate them into individual semiconductor packages. Is manufactured.

특히, 상기 몰딩공정은 첨부한 도 8에 도시한 바와 같이, 수지(34)가 채워지는 캐비티(42)가 상면 중앙에 형성되고, 이 캐비티(42)의 중앙에 수지공급구(44)가 형성된 형태의 하형(20)과; 이 하형(20)의 상면에 밀착되며 클램핑되는 평평한 형태의 상형(19)으로 구성된 몰딩다이(18)를 사용하여 진행하게 된다.In particular, in the molding step, as shown in FIG. 8, a cavity 42 filled with the resin 34 is formed in the center of the upper surface, and a resin supply port 44 is formed in the center of the cavity 42. A lower mold 20 of the form; It proceeds using the molding die 18 which consists of the upper mold | type 19 of the flat form clamped on the upper surface of the lower mold | type 20, and clamped.

이에, 상기 하형(20)에 부재(10c)를 안착시키게 되면, 부재(10c)의 각 몰딩영역이 하형(20)의 캐비티(42)와 일치되며 안착되는 바, 상기 수지공급구(44)를 통하여 수지(34)가 캐비티(42)로 공급되어, 부재(10c)의 각 몰딩영역이 개별적으로 몰딩되어진다.Therefore, when the member 10c is seated on the lower mold 20, each molding region of the member 10c is aligned with the cavity 42 of the lower mold 20, and thus the resin supply hole 44 is mounted. The resin 34 is supplied to the cavity 42 through the respective molding regions, and each molding region of the member 10c is molded separately.

그러나, 상기와 같은 칩 스케일 반도체 패키지 제조용 부재는 다음과 같은단점이 있다.However, such a chip scale semiconductor package manufacturing member has the following disadvantages.

즉, 각 반도체 패키지 영역이 타이바로 연결됨에 따라, 각 사이에는 슬롯홀이 형성되어, 보다 조밀한 반도체 패키지 영역을 설계하는데 한계가 있고, 부재의 각 몰딩영역을 개별적으로 몰딩해주기 때문에 시간당 단위생산성이 떨어지는 단점이 있다.That is, as each semiconductor package region is connected by a tie bar, slot holes are formed between each one, which limits the design of a more dense semiconductor package region. Since each molding region of the member is molded separately, unit productivity per hour is increased. There is a downside to falling.

따라서, 본 발명은 상기와 같은 칩 스케일의 반도체 패키지 제조용 부재의 단점을 보완하고자 안출한 것으로서, 다수의 반도체 패키지 영역을 매트릭스 배열로 형성하된, 부재의 각 반도체 패키지 영역의 양쪽에 인출단자 부착용 랜드를 배열시키는 동시에 랜드의 안쪽 영역을 몰딩영역으로 형성한 구조의 반도체 패키지 제조용 부재와, 이렇게 구성된 다수의 반도체 패키지 영역중 일렬을 하나의 그룹으로 설정하여, 이 그룹으로 설정된 반도체 패키지 영역내의 몰딩영역을 한꺼번에 몰딩할 수 있도록 함으로써, 다수의 반도체 패키지 영역을 조밀하게 유지하는 동시에 반도체 패키지로 제조후 적층이 가능하도록 한 반도체 패키지 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above disadvantages of the chip-scale semiconductor package manufacturing member, the land for attaching the lead-out terminal on both sides of each semiconductor package region of the member, formed in a matrix array of a plurality of semiconductor package region The semiconductor package fabrication member having a structure in which the inner region of the land is formed as a molding region, and a line of the plurality of semiconductor package regions thus configured are set as a group to form a molding region in the semiconductor package region set in this group. It is an object of the present invention to provide a method of manufacturing a semiconductor package, which allows molding at a time, thereby maintaining a plurality of semiconductor package regions densely, and enabling lamination after fabrication into a semiconductor package.

도 1은 본 발명에 따른 반도체 패키지 제조용 부재를 나타내는 평면도,1 is a plan view showing a member for manufacturing a semiconductor package according to the present invention,

도 2는 본 발명에 따른 반도체 패키지 제조용 부재를 이용한 반도체 패키지의 몰딩공정을 나타내는 단면도,2 is a cross-sectional view showing a molding process of a semiconductor package using a member for manufacturing a semiconductor package according to the present invention;

도 3은 본 발명의 반도체 패키지를 나타내는 단면도,3 is a cross-sectional view showing a semiconductor package of the present invention;

도 4는 종래의 반도체 패키지의 몰딩된 상태를 나타내는 평면도,4 is a plan view illustrating a molded state of a conventional semiconductor package;

도 5는 도 4의 반도체 패키지를 나타내는 단면도,5 is a cross-sectional view illustrating the semiconductor package of FIG. 4;

도 6은 종래의 또 다른 반도체 패키지의 몰딩된 상태를 나타내는 평면도,6 is a plan view showing a molded state of another conventional semiconductor package;

도 7은 도 6의 반도체 패키지를 나타내는 단면도.FIG. 7 is a sectional view of the semiconductor package of FIG. 6; FIG.

도 8은 도 6의 반도체 패키지의 몰딩공정을 나타내는 단면도.8 is a cross-sectional view illustrating a molding process of the semiconductor package of FIG. 6.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10a,10b,10c : 부재 12 : 반도체 패키지 영역10a, 10b, 10c: member 12: semiconductor package region

14 : 인출단자 부착용 랜드 16 : 몰딩영역14: land for attaching outgoing terminal 16: molding area

18 : 몰딩다이 19 : 상형18: Molding Die 19: Pictograph

20 : 하형 22 : 수지층20: lower mold 22: resin layer

24 : 전도성패턴 26 : 커버코트24: conductive pattern 26: cover coat

28 : 반도체 칩 30 : 접착수단28 semiconductor chip 30 bonding means

32 : 와이어 34 : 수지32: wire 34: resin

36 : 솔더볼 38 : 타이바36: solder ball 38: tie bar

40 : 칩 부착용 홀 42 : 캐비티40: chip mounting hole 42: cavity

44 : 수지공급구44: resin supply port

상기한 목적을 달성하기 위한 본 발명의 부재는:The members of the present invention for achieving the above object are:

중앙에 칩부착용 홀이 형성되고 다수의 반도체 패키지 영역이 매트릭스 배열을 이루며 형성된 반도체 패키지 제조용 부재에 있어서,In the semiconductor package manufacturing member formed with a chip attaching hole in the center and a plurality of semiconductor package regions in a matrix arrangement,

상기 각 반도체 패키지 영역의 양쪽에 인출단자 부착용 랜드를 형성하고, 상기 칩 부착용 홀을 포함하는 상기 인출단자 부착용 랜드의 안쪽영역을 몰딩영역으로 형성한 것을 특징으로 한다.The land for attaching the outgoing terminal is formed on both sides of each of the semiconductor package regions, and an inner region of the land for attaching the outgoing terminal including the chip attaching hole is formed as a molding region.

바람직한 구현예로서, 상기 각 반도체 패키지 영역 라인은 싱귤레이션 라인이 되는 것을 특징으로 한다.In a preferred embodiment, each of the semiconductor package region lines is a singulation line.

상기한 목적을 달성하기 위한 본 발명의 방법은:The method of the present invention for achieving the above object is:

상기 다수의 반도체 패키지 영역중 일렬을 하나의 그룹으로 설정하여, 이 그룹에 해당되는 반도체 패키지 영역내의 몰딩영역으로 수지를 수평방향으로 공급하여, 상기 그룹내의 몰딩영역이 차례대로 몰딩되도록 한 것을 특징으로 한다.A line of the plurality of semiconductor package regions is set as a group, and resin is horizontally supplied to a molding region in the semiconductor package region corresponding to the group so that the molding regions in the group are molded in sequence. do.

여기서 본 발명의 실시예를 첨부한 도면에 의거하여 보다 상세하게 설명하면 다음과 같다.Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도 1은 본 발명에 따른 반도체 패키지 제조용 부재를 나타내는 평면도로서, 상기 부재(10a)는 다수의 반도체 패키지 영역(12)이 매트릭스 배열을 이루며 형성된 인쇄회로기판이며, 베이스층인 수지층(22)과, 수지층(22)상에 식각처리된 전도성패턴(24)과, 이 전도성패턴중 와이어 및 인출단자 부착용 전도성패턴을 외부로 노출시키며 수지층상에 도포된 커버코트(26)로 구성되어 있다.1 is a plan view illustrating a member for manufacturing a semiconductor package according to the present invention, wherein the member 10a is a printed circuit board in which a plurality of semiconductor package regions 12 are formed in a matrix arrangement, and the resin layer 22 is a base layer. ), A conductive pattern 24 etched on the resin layer 22, and a cover coat 26 coated on the resin layer while exposing the conductive patterns for attaching wires and lead terminals among the conductive patterns to the outside. .

상기 부재(10a)의 각 반도체 패키지 영역(12)에는 칩 부착용 홀(40)이 형성되어 있고, 그 양쪽으로는 인출단자 부착용 랜드(14)가 등간격으로 배열되어 있다.In each semiconductor package region 12 of the member 10a, a chip attaching hole 40 is formed, and on both sides thereof, lands 14 for attaching terminals are arranged at equal intervals.

이때, 상기 칩 부착용 홀(40)을 포함하는 인출단자 부착용 랜드(14)의 안쪽영역은 몰딩영역(16)으로 형성된다.In this case, the inner region of the land for attaching the terminal 14 including the chip attaching hole 40 is formed as a molding region 16.

바람직한 구현예로서, 상기 부재(10a)는 반도체 패키지의 적층을 위하여, 양면으로 인출단자 부착용 랜드(14)가 형성되도록 한다.In a preferred embodiment, the member 10a allows the lands 14 for attaching the drawing terminals to be formed on both surfaces thereof in order to stack the semiconductor package.

상기와 같은 구조로 이루어진 본 발명의 부재를 이용하여 반도체 패키지 제조하는 방법을 첨부한 도 3을 참조로 설명하면 다음과 같다.Referring to Figure 3 attached to a method for manufacturing a semiconductor package using the member of the present invention having the above structure as follows.

먼저, 상기 부재(10a)의 일면에 칩 부착용 홀(40)을 마감시키며 접착테이프를 부착하는 단계와; 상기 칩 부착용 홀(40)내로 반도체 칩(28)을 픽업하여 접착테이프상에 부착시키는 단계와; 상기 반도체 칩(28)의 본딩패드와 부재의 와이어 본딩용 전도성패턴간을 와이어(32)로 본딩하는 단계를 진행시킨다.First, attaching an adhesive tape while closing the chip attachment hole 40 on one surface of the member (10a); Picking up and attaching the semiconductor chip 28 into the chip attaching hole 40 on the adhesive tape; Bonding between the bonding pad of the semiconductor chip 28 and the conductive pattern for wire bonding of the member with the wire 32 is performed.

다음으로, 상기 칩 부착 공정과 와이어 본딩 공정을 마친 반도체 패키지 제조용 부재(10a)의 몰딩영역(16)을 수지(34)로 몰딩하는 단계를 진행하는 바, 다수의 반도체 패키지 영역(12)중 일렬을 하나의 그룹으로 설정하여, 이 그룹에 해당되는 반도체 패키지 영역(12)내의 몰딩영역(16)이 한꺼번에 몰딩되도록 한다.Next, molding the molding region 16 of the member 10a for manufacturing the semiconductor package after the chip attaching process and the wire bonding process is performed with the resin 34, thereby forming a line of the plurality of semiconductor package regions 12. Is set to one group so that the molding region 16 in the semiconductor package region 12 corresponding to this group is molded at once.

즉, 첨부한 도 2에 도시한 바와 같이, 상기 칩 부착 공정과 와이어 본딩 공정을 마친 부재(10a)를 평평한 형태로 된 몰딩다이(18)의 하형(20)에 안착시킨 후, 몰딩다이(18)의 상형(19)을 클램핑시키면, 하나의 그룹으로 설정된 반도체 패키지 영역(12)의 몰딩영역(16)은 상기 상형(19)의 캐비티(42)와 상하로 일치하게 된다.That is, as shown in FIG. 2, after the chip attaching process and the wire bonding process are completed, the member 10a is seated on the lower mold 20 of the molding die 18 having a flat shape, and then the molding die 18 is formed. When the upper die 19 is clamped, the molding region 16 of the semiconductor package region 12 set as a group coincides with the cavity 42 of the upper die 19.

따라서, 상기 상형(19)의 캐비티(42)로 수지(34)를 소정의 압으로 공급하게 되면, 하나의 그룹으로 설정된 반도체 패키지 영역(12)의 몰딩영역(16)이 한꺼번에 몰딩되어진다.Therefore, when the resin 34 is supplied to the cavity 42 of the upper mold 19 at a predetermined pressure, the molding regions 16 of the semiconductor package regions 12 set as one group are molded at once.

좀 더 상세하게는, 상기 상형(19)의 각 캐비티(42)로 수지(34)가 수평방향으로 공급되어, 상기 그룹내의 각 몰딩영역(16)이 차례로 몰딩되어진다.More specifically, the resin 34 is supplied in the horizontal direction to each cavity 42 of the upper die 19 so that each molding region 16 in the group is molded in turn.

한편, 상기 각 반도체 패키지 영역(12) 라인은 싱귤레이션 라인이 된다.Meanwhile, each of the semiconductor package region 12 lines is a singulation line.

다음으로, 상기 인출단자 부착용 랜드(14)에 전도성의 솔더볼(36)을 융착시킨 후, 상기 싱귤레이션 라인을 따라 펀칭수단 또는 블레이드와 같은 소잉수단을 사용하여 낱개의 반도체 패키지로 싱귤레이션 함으로써, 첨부한 도 3에 도시한 바와 같은 구조의 반도체 패키지(100)로 제조된다.Next, the conductive solder ball 36 is fused to the lead terminal attaching land 14, and then singulated into a single semiconductor package using a sawing means such as a punching means or a blade along the singulation line. A semiconductor package 100 having a structure as shown in FIG. 3 is manufactured.

이때, 상기 반도체 패키지(100)를 적층하고자 할때에는, 부재(10a)의 저면으로도 인출단자 부착용 랜드(14)를 노출시켜, 이곳으로 하부쪽에 적층되는 패키지의 솔더볼(36)이 융착되도록 하면 된다.In this case, when the semiconductor package 100 is to be stacked, the land for attaching the terminal 14 may also be exposed to the bottom surface of the member 10a so that the solder balls 36 of the package stacked on the lower side may be fused. .

이상에서 본 바와 같이, 본 발명에 따른 반도체 패키지 제조용 부재와 이것을 이용한 반도체 패키지 제조방법에 의하면 부재상에 반도체 패키지 영역을 조밀하게 최대로 수용할 수 있고, 몰딩공정이 일렬의 반도체 패키지 영역에 대하여 이루어져 단위생산성을 향상시킬 수 있으며, 반도체 패키지로 제조후, 적층을 가능하게 할 수 있는 잇점이 있다.As described above, according to the semiconductor package manufacturing member and the semiconductor package manufacturing method using the same according to the present invention, the semiconductor package region can be densely accommodated on the member to the maximum, and a molding process is performed for the semiconductor package region in a row. Unit productivity can be improved, and after manufacturing with a semiconductor package, lamination can be made possible.

Claims (3)

중앙에 칩부착용 홀이 형성되고 다수의 반도체 패키지 영역이 매트릭스 배열을 이루며 형성된 반도체 패키지 제조용 부재에 있어서,In the semiconductor package manufacturing member formed with a chip attaching hole in the center and a plurality of semiconductor package regions in a matrix arrangement, 상기 각 반도체 패키지 영역에서 칩부착용 홀의 양쪽에 인출단자 부착용 랜드를 형성하고, 상기 칩 부착용 홀을 포함하는 상기 인출단자 부착용 랜드의 안쪽영역을 몰딩영역으로 형성하며, 각 반도체 패키지 영역은 낱개의 반도체 패키지로 절단하는 싱귤레이션 라인이 되도록 한 것을 특징으로 하는 반도체 패키지 제조용 부재.A land for attaching the outgoing terminal is formed in each of the chip attaching holes in each semiconductor package region, and an inner region of the land for attaching the outgoing terminal including the chip attaching hole is formed as a molding region, and each semiconductor package region is a single semiconductor package. A member for manufacturing a semiconductor package, characterized in that it becomes a singulation line to be cut by a. 삭제delete 다수의 반도체 패키지 영역이 매트릭스 배열을 이루되, 각 반도체 패키지 영역에서 인출단자 부착용 랜드의 안쪽영역이 몰딩영역으로 형성된 구조의 부재를 제공하는 단계와; 이 부재에서 일렬의 반도체 패키지 영역을 하나의 그룹으로 설정하여, 이 그룹에 해당되는 반도체 패키지 영역내의 몰딩영역이 몰딩다이의 캐비티와 일치되도록 안착시키는 단계와; 상기 몰딩다이의 캐비티에 수지를 수평방향으로 공급하여, 상기 그룹내의 몰딩영역이 차례대로 몰딩되도록 한 것을 특징으로 하는 반도체 패키지 제조방법.Providing a member having a structure in which a plurality of semiconductor package regions form a matrix arrangement, in which the inner region of the land for attaching the extracting terminal is formed as a molding region in each semiconductor package region; Setting a row of semiconductor package regions in the member as a group, and seating the molding regions in the semiconductor package regions corresponding to the group coincide with the cavities of the molding die; And supplying resin to the cavity of the molding die in a horizontal direction so that molding regions in the group are molded in sequence.
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JPH08213416A (en) * 1995-01-27 1996-08-20 Nec Corp Lead frame for semiconductor device and molding machine using the same
KR980007939A (en) * 1996-06-21 1998-03-30 황인길 Molding method of BGA package with heat sink
KR19990043139A (en) * 1997-11-28 1999-06-15 김규현 Mold mold of chip array ball grid array package and mold structure using same
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JPH08213416A (en) * 1995-01-27 1996-08-20 Nec Corp Lead frame for semiconductor device and molding machine using the same
KR980007939A (en) * 1996-06-21 1998-03-30 황인길 Molding method of BGA package with heat sink
KR19990043139A (en) * 1997-11-28 1999-06-15 김규현 Mold mold of chip array ball grid array package and mold structure using same
US6111324A (en) * 1998-02-05 2000-08-29 Asat, Limited Integrated carrier ring/stiffener and method for manufacturing a flexible integrated circuit package
KR20000019511U (en) * 1999-04-14 2000-11-15 마이클 디. 오브라이언 printed circuit board for semi-conductor package

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