KR100361988B1 - Substrate for manufacturing semiconductor package and method for manufacturing semiconductor package using the same - Google Patents
Substrate for manufacturing semiconductor package and method for manufacturing semiconductor package using the same Download PDFInfo
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- KR100361988B1 KR100361988B1 KR1020010007083A KR20010007083A KR100361988B1 KR 100361988 B1 KR100361988 B1 KR 100361988B1 KR 1020010007083 A KR1020010007083 A KR 1020010007083A KR 20010007083 A KR20010007083 A KR 20010007083A KR 100361988 B1 KR100361988 B1 KR 100361988B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
본 발명은 반도체 패키지 영역이 매트릭스 배열로 형성된 반도체 패키지 제조용 부재와 이것을 이용한 반도체 패키지 제조방법에 관한 것으로서, 각각의 반도체 패키지 영역의 두 개의 전체 변과, 나머지 두 개의 변에서 양끝 일부분에 걸쳐 서로 연통되는 슬롯홀이 형성되고, 상기 반도체 패키지 영역의 중앙에 형성된 칩탑재영역의 두 개의 변에서 바로 인접된 곳에 와이어 본딩용 전도성패턴이 배열되며, 상기 와이어 본딩용 전도성패턴과 상기 슬롯홀 사이의 영역에 걸쳐 다수개의 인출단자 부착용 랜드가 소정의 배열로 형성되며, 상기 각 반도체 패키지 영역의 슬롯홀이 형성되지 않은 중간 부분은 몰딩수지 흐름용 게이트면이 되는 동시에 펀칭영역으로 설정된 것을 특징으로 하는 반도체 패키지 제조용 부재와;BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package manufacturing member having a semiconductor package region formed in a matrix array and a semiconductor package manufacturing method using the same. A slot hole is formed, and a wire bonding conductive pattern is arranged directly adjacent to two sides of the chip mounting region formed in the center of the semiconductor package region, and is disposed over the region between the wire bonding conductive pattern and the slot hole. A plurality of lead-out terminal attaching lands are formed in a predetermined arrangement, and the intermediate portion, in which the slot holes of each semiconductor package region are not formed, becomes a gate surface for molding resin flow and is set as a punching region. Wow;
상기 매트릭스 배열을 이루고 있는 다수의 반도체 패키지 영역중 하나의 열을 한꺼번에 몰딩하되, 순차적으로 몰딩하고, 각 반도체 패키지 영역이 펀칭에 의하여 한꺼번에 싱귤레이션될 수 있도록 한 단계를 특징하는 반도체 패키지 제조 방법을 제공하고자 한 것이다.A method of manufacturing a semiconductor package, the method comprising: molding one row of a plurality of semiconductor package regions forming the matrix array at a time, molding sequentially, and allowing each semiconductor package region to be singulated at once by punching It would be.
Description
본 발명은 반도체 패키지 제조용 부재 및 이것을 이용한 반도체 패키지 제조방법에 관한 것으로서, 더욱 상세하게는 다수의 반도체 패키지 영역이 매트릭스 배열로 형성된 반도체 패키지 제조용 부재에 있어서, 각각의 반도체 패키지 영역내의 몰딩영역을 순차적으로 한꺼번에 몰딩하고, 각 반도체 패키지 영역이 펀칭에 의하여 한꺼번에 싱귤레이션 될 수 있도록 한 구조의 반도체 패키지 제조용 부재 및 이것을 이용한 반도체 패키지 제조방법에 관한 것이다.The present invention relates to a semiconductor package manufacturing member and a semiconductor package manufacturing method using the same. More particularly, in a semiconductor package manufacturing member having a plurality of semiconductor package regions formed in a matrix array, molding regions in each semiconductor package region are sequentially The present invention relates to a member for manufacturing a semiconductor package having a structure which is molded at a time, and that each semiconductor package region can be singulated at once by punching, and a method for manufacturing a semiconductor package using the same.
통상적으로 반도체 패키지는 리드프레임, 인쇄회로기판, 회로필름등과 같은 각종 부재를 이용하여 다양한 구조로 제조되고 있는 바, 최근에는 칩 스케일 패키지(CSP:Chip Scale Package)라 하여, 반도체 패키지가 반도체 칩의 크기에 가깝게경박단소화로 제조되는 추세에 있다.In general, semiconductor packages are manufactured in various structures using various members such as lead frames, printed circuit boards, and circuit films. Recently, semiconductor packages are referred to as chip scale packages (CSPs). There is a tendency to be manufactured by reducing the size of thin.
대개, 상기 칩 스케일의 반도체 패키지를 제조하기 위한 인쇄회로기판 부재에는 반도체 패키지 영역이 설계에 따라 3×4, 4×4 등의 매트릭스 배열을 이루며 매우 조밀하게 형성되어 있다.Usually, in the printed circuit board member for manufacturing the chip scale semiconductor package, the semiconductor package region is formed very densely in a matrix arrangement of 3x4, 4x4, etc. according to the design.
여기서, 칩 스케일 패키지의 하나의 예로서, 상기 반도체 패키지 제조용 부재를 사용하여 그 제조 방법을 도 5를 참조로 간략히 설명하면 다음과 같다.Here, as an example of a chip scale package, a method of manufacturing the same using the semiconductor package manufacturing member will be briefly described with reference to FIG. 5 as follows.
상기 부재(10b)는 인쇄회로기판으로서, 베이스층인 수지층(22)과; 이 수지층상에 식각 처리된 전도성패턴(24)과; 이 전도성패턴(24)들중 인출단자 부착용 전도성패턴과 와이어 본딩용 전도성패턴을 노출시키면서 상기 수지층(22)상에 도포된 커버코트(26)로 구성되어 있다.The member 10b is a printed circuit board, which includes a resin layer 22 serving as a base layer; A conductive pattern 24 etched on the resin layer; The conductive pattern 24 is composed of a cover coat 26 coated on the resin layer 22 while exposing the conductive terminal attaching pattern and the wire bonding conductive pattern.
따라서, 상기 부재(10b)상에 매트릭스 배열을 이루고 있는 각 반도체 패키지 영역의 칩탑재영역에 반도체 칩(28)을 접착수단으로 부착하는 단계와; 상기 반도체 칩(28)의 본딩패드와 부재(10b)의 와이어 본딩용 전도성패턴간을 와이어(32)로 본딩하는 단계와; 상기 반도체 칩(28)과 와이어(32)등을 포함하는 각 반도체 패키지의 몰딩영역을 한꺼번에 수지(34)로 몰딩하는 단계와; 상기 인출단자 부착용 전도성패턴에 전도성의 솔더볼(36)을 부착하는 단계와; 상기 각각의 반도체 패키지 영역을 블레이드와 같은 소잉수단을 사용하여 낱개의 반도체 패키지로 싱귤레이션하는 단계등을 거쳐, 첨부한 도 5에 도시한 바와 같은 구조의 반도체 패키지(200)로 제조되어진다.Therefore, attaching the semiconductor chip 28 to the chip mounting region of each semiconductor package region in a matrix arrangement on the member 10b by an adhesive means; Bonding between the bonding pad of the semiconductor chip 28 and the conductive pattern for wire bonding of the member 10b with a wire 32; Molding a molding region of each semiconductor package including the semiconductor chip 28, the wire 32, and the like with resin 34 at one time; Attaching a conductive solder ball 36 to the conductive terminal attachment pattern; Each semiconductor package region is manufactured into a semiconductor package 200 having a structure as shown in FIG.
보다 상세하게는 상기 몰딩공정에 있어서, 인쇄회로기판상의 매트릭스 배열로 이루어진 각각의 반도체 패키지 영역이 한꺼번에 수지로 몰딩되고, 상기 반도체 패키지 영역 라인(=싱귤레이션 라인)을 따라 블레이드와 같은 소잉수단으로 소잉을 함으로써, 낱개의 반도체 패키지로 싱귤레이션되어진다.More specifically, in the molding process, each semiconductor package region formed of a matrix array on a printed circuit board is molded with resin at once, and sawed by sawing means such as a blade along the semiconductor package region line (= singulation line). By doing so, it is singulated into a single semiconductor package.
그러나, 상기 싱귤레이션 공정시 블레이드에 의한 소잉 방법은 가로 및 세로 방향의 싱귤레이션 라인을 따라 블레이드를 구동시켜 소잉을 함에 따라, 작업시간이 오래 걸리고, 그에따라 작업시간 대비 낱개로 싱귤레이션되는 반도체 패키지의 생산수가 적어 단위 생산성이 떨어지는 단점이 있고, 블레이드의 마모에 따른 교체비용등 소잉시의 부대 비용이 많이드는 단점이 있다.However, the sawing method by the blade in the singulation process is a semiconductor package that takes a long time, and accordingly singularly compared to the working time as the sawing by driving the blades along the horizontal and vertical singulation lines There is a disadvantage in that the unit productivity is low due to the small number of production, there is a disadvantage in that the additional cost at the time of sawing, such as replacement cost due to wear of the blade.
본 발명은 상기와 같은 점을 감안하여, 종래에 블레이드에 의한 싱귤레이션 공정을 배제하고, 펀칭에 의하여 많은 수의 반도체 패키지를 한꺼번에 싱귤레이션할 수 있도록 몰딩구조와 싱귤레이션 영역의 구조를 개선한 반도체 패키지 제조용 부재 및 이것을 이용한 반도체 패키지 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION In view of the above, the present invention eliminates the singulation process by blades in the related art and improves the structure of the molding structure and the singulation region so that a large number of semiconductor packages can be singulated at once by punching. An object of the present invention is to provide a package manufacturing member and a semiconductor package manufacturing method using the same.
이에, 펀칭에 의하여 다수의 반도체 패키지가 동시에 싱귤레이션되어, 시간당 단위생산성을 크게 향상시킬 수 있게 된다.Accordingly, by punching, a plurality of semiconductor packages are singulated at the same time, thereby greatly improving unit productivity per hour.
도 1은 본 발명에 따른 반도체 패키지 제조용 부재를 나타내는 평면도,1 is a plan view showing a member for manufacturing a semiconductor package according to the present invention,
도 2는 도 1의 A-A선 단면도,2 is a cross-sectional view taken along the line A-A of FIG.
도 3은 본 발명에 따른 반도체 패키지 제조용 부재를 사용하여 반도체 패키지를 제조함에 있어서, 몰딩공정을 나타내는 단면도,3 is a cross-sectional view showing a molding process in manufacturing a semiconductor package using a member for manufacturing a semiconductor package according to the present invention;
도 4a,4b는 본 발명에 따른 부재를 사용하여 제조된 반도체 패키지를 나타내는 단면도,4A and 4B are cross-sectional views showing a semiconductor package manufactured using the member according to the present invention;
도 5는 종래에 칩 스케일로 제조되는 반도체 패키지의 일례를 나타내는 단면도.5 is a cross-sectional view showing an example of a semiconductor package conventionally manufactured on a chip scale.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10a,10b : 부재 12 : 반도체 패키지 영역10a, 10b: member 12: semiconductor package region
14 : 슬롯홀 16 : 인출단자 부착용 랜드14: slot hole 16: land for attaching outgoing terminal
18 : 게이트면 19 : 칩탑재영역18: gate surface 19: chip mounting area
20 : 몰딩영역 21 : 런너면20: molding area 21: runner surface
22 : 수지층 24 : 전도성패턴22: resin layer 24: conductive pattern
26 : 커버코트 28 : 반도체 칩26 cover coat 28 semiconductor chip
30 : 접착수단 31 : 와이어 본딩용 전도성패턴30: bonding means 31: conductive pattern for wire bonding
32 : 와이어 34 : 수지32: wire 34: resin
36 : 솔더볼 40 : 몰딩다이36: solder ball 40: molding die
42 : 상형 44 : 하형42: upper mold 44: lower mold
46 : 캐비티 48 : 런너공간46: cavity 48: runner space
상기한 목적을 달성하기 위한 본 발명의 부재는:The members of the present invention for achieving the above object are:
다수의 반도체 패키지 영역이 매트릭스 배열로 형성된 반도체 패키지 제조용부재에 있어서, 상기 각각의 반도체 패키지 영역(12)의 종방향 두 개의 전체 변과, 나머지 횡방향 두 개의 변에서 양끝 일부분에 걸쳐 서로 연통되는 슬롯홀(14)이 형성되고; 상기 반도체 패키지 영역(12)의 중앙에 천공홀 형태로 형성되어 접착수단(30)이 부착되는 칩탑재영역(19)의 종방향 두 개의 변에서 바로 인접된 곳에 와이어 본딩용 전도성패턴(31)이 배열되며; 상기 와이어 본딩용 전도성패턴(31)과 상기 종방향의 슬롯홀(14) 사이의 영역에 걸쳐 다수개의 인출단자 부착용 랜드(16)가 소정의 배열로 형성되며; 상기 각 반도체 패키지 영역(12)의 횡방향 변에서 슬롯홀이 형성되지 않은 중간 부분은 몰딩수지 흐름용 게이트면(18)이 되는 동시에 펀칭영역으로 설정된 것을 특징으로 한다.In a semiconductor package manufacturing member in which a plurality of semiconductor package regions are formed in a matrix arrangement, slots which communicate with each other over both ends of two longitudinal sides of each semiconductor package region 12 and two end portions of the remaining two horizontal sides. A hole 14 is formed; The conductive pattern 31 for wire bonding is formed in the center of the semiconductor package region 12 in the form of a perforation hole and immediately adjacent to two longitudinal sides of the chip mounting region 19 to which the adhesive means 30 is attached. Arranged; A plurality of lead terminal attaching lands 16 are formed in a predetermined arrangement over an area between the wire bonding conductive pattern 31 and the longitudinal slot hole 14; The intermediate portion of the semiconductor package region 12 in which the slot holes are not formed at the lateral side thereof becomes the punching region at the same time as the gate surface 18 for the molding resin flow.
바람직한 구현예로서, 상기 몰딩수지 흐름용 게이트면(18)과 인출단자 부착용 랜드(16)가 형성된 영역의 안쪽영역은 상기 칩탑재영역(19)과 와이어 본딩용 전도성패턴(31)을 포함하는 몰딩영역(20)이 되는 것을 특징으로 한다.In a preferred embodiment, the inner region of the region where the molding resin flow gate surface 18 and the lead terminal attaching land 16 is formed includes the chip mounting region 19 and the conductive pattern 31 for wire bonding. The area 20 is characterized in that.
특히, 상기 몰딩수지 흐름용 게이트면(18)의 사이 영역은 몰딩수지의 흐름 을 유도하기 위한 런너면(21)으로 형성된 것을 특징으로 한다.In particular, the region between the molding resin flow gate surface 18 is characterized by being formed with a runner surface 21 for inducing the flow of the molding resin.
상기한 목적을 달성하기 위한 본 발명의 방법은:The method of the present invention for achieving the above object is:
다수의 반도체 패키지 영역이 매트릭스 배열로 형성되되, 각각의 반도체 패키지 영역(12)의 종방향 두 개의 전체 변과 나머지 횡방향 두 개의 변의 양끝 일부분에 걸쳐 서로 연통되는 슬롯홀(14)이 형성되고, 상기 각 반도체 패키지 영역(12)의 종방향 변에서 슬롯홀이 형성되지 않은 중간 부분은 몰딩수지 흐름용 게이트면(18)이 되며, 이 몰딩수지 흐름용 게이트면(18)의 사이 영역은 몰딩수지의흐름을 유도하는 런너면(21)으로 형성된 구조의 부재(10a)를 제공하는 단계와; 상기 각 반도체 패키지 영역(12)의 칩탑재영역(19)에 부착되어 있는 접착수단에 반도체 칩(28)을 부착하는 단계와; 상기 반도체 칩(28)의 본딩패드와, 상기 칩탑재영역(19)의 종방향 두 개의 변과 인접되게 형성된 와이어 본딩용 전도성패턴(31)간을 와이어(32)로 연결하는 단계와; 상기 부재(10a)의 런너면(21)이 형성된 방향으로 배열되어 있는 다수개의 반도체 패키지 영역(12)을 하나의 열로 설정하고, 이 반도체 패키지 영역(12)내의 몰딩영역(20)을 몰딩다이(40)로 한꺼번에 클램핑하는 단계와; 상기 몰딩다이(40)의 수지공급구를 통하여 수지(34)를 측방향에서 공급하는 동시에 수지(34)가 상기 각 반도체 패키지 영역(12)의 몰딩수지 흐름용 런너면(21)과 게이트면(18)를 따라 각 몰딩영역(20)으로 순차적으로 흘러서, 상기 각 몰딩영역(20)내의 반도체 칩(28)과, 와이어(32)와, 와이어 본딩용 전도성패턴(31)이 몰딩되도록 한 단계와; 상기 부재(10a)의 인출단자 부착용 랜드(16)에 전도성의 인출단자(36)를 융착하는 단계와; 상기 부재(10a)의 각 몰딩수지 흐름용 게이트면(18)를 펀칭수단으로 펀칭을 하여, 낱개 단위의 반도체 패키지(100)로 싱귤레이션하는 단계로 이루어진 것을 특징으로 한다.A plurality of semiconductor package regions are formed in a matrix arrangement, and slot holes 14 are formed to communicate with each other over portions of both ends of two longitudinal sides of each semiconductor package region 12 and both ends of the remaining two transverse sides. The intermediate portion of the semiconductor package region 12 in which the slot hole is not formed at the longitudinal side thereof becomes the molding resin flow gate surface 18, and the region between the molding resin flow gate surfaces 18 is the molding resin. Providing a member (10a) having a structure formed of a runner surface (21) for inducing flow; Attaching a semiconductor chip (28) to bonding means attached to the chip mounting region (19) of each of the semiconductor package regions (12); Connecting a bonding pad of the semiconductor chip 28 with a wire bonding conductive pattern 31 formed adjacent to two longitudinal sides of the chip mounting region 19 with a wire 32; A plurality of semiconductor package regions 12 arranged in the direction in which the runner surface 21 of the member 10a is formed is set in one row, and the molding region 20 in the semiconductor package region 12 is formed by a molding die ( Clamping all at once; The resin 34 is supplied laterally through the resin supply port of the molding die 40, and the resin 34 has a runner surface 21 and a gate surface for molding resin flow in each of the semiconductor package regions 12. 18 sequentially flowing to each molding region 20 so that the semiconductor chip 28, the wire 32, and the wire bonding conductive pattern 31 in each molding region 20 are molded. ; Fusing a conductive lead terminal (36) to the lead terminal attachment land (16) of the member (10a); Punching each of the molding resin flow gate surface 18 of the member (10a) by a punching means, it characterized in that it comprises a step of singulation into the semiconductor package 100 of each unit.
한편, 상기 클램핑 단계시, 부재(10a)를 몰딩다이(40)의 하형(44)에 안착시키고, 몰딩다이(40)의 상형(42)을 클램핑시킬 때, 상기 상형(42)에 형성된 각 캐비티(46)와, 상기 반도체 칩(28)과 와이어(32)와 와이어 본딩용 전도성패턴(31)을 포함하는 부재(10a)의 각 몰딩영역(20)이 상하로 일치되도록 하고, 상기 상형(42)의 각 캐비티(46) 사이에 형성된 런너공간(48)이 상기 부재(10a)의 몰딩수지 흐름용런너면(21)과 상하로 일치되도록 함을 특징으로 한다.Meanwhile, in the clamping step, when the member 10a is seated on the lower mold 44 of the molding die 40, and the upper mold 42 of the molding die 40 is clamped, each cavity formed in the upper mold 42 is formed. 46 and the molding region 20 of the member 10a including the semiconductor chip 28, the wire 32, and the conductive pattern 31 for wire bonding are vertically aligned, and the upper mold 42 Runner space 48 formed between the cavities 46 of the c) is coincident with the molding resin flow runner face 21 of the member 10a.
여기서 본 발명의 실시예를 첨부한 도면에 의거하여 보다 상세하게 설명하면 다음과 같다.Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도 1은 본 발명에 따른 반도체 패키지 제조용 부재를 나타내는 평면도로서, 상기 부재(10a)는 다수의 반도체 패키지 영역(12)이 매트릭스 배열로 형성되어 있는 인쇄회로기판이다.1 is a plan view showing a member for manufacturing a semiconductor package according to the present invention, wherein the member 10a is a printed circuit board in which a plurality of semiconductor package regions 12 are formed in a matrix arrangement.
본 발명의 주된 특징으로서, 상기 각각의 반도체 패키지 영역(12)의 외곽라인을 따라서 서로 연통된 슬롯홀(14)이 형성되는 바, 이 슬롯홀(14)은 종방향 두 개의 변 전체에 관통되게 형성되고, 나머지 횡방향 두 개의 변에서 중간부분을 제외한 양쪽 끝 일부분에까지 연장되어 형성된다.As a main feature of the present invention, slot holes 14 communicating with each other are formed along the outer line of each semiconductor package region 12, so that the slot holes 14 penetrate through the two longitudinal sides. It extends to both end portions except the middle portion in the remaining two transverse sides.
이때, 상기 슬롯홀(14)이 형성되지 않은 횡방향 두 개의 변의 중간부분은 첨부한 도 3에 도시한 바와 같이, 몰딩수지 흐름용 게이트면(18)으로 형성되고, 나중에 펀칭에 의하여 제거되는 펀칭영역이 되기도 한다.At this time, the middle portion of the two sides in the lateral direction in which the slot hole 14 is not formed is formed as the gate surface 18 for the molding resin flow, as shown in FIG. 3, which is later removed by punching. It can also be a realm.
또한, 상기 각 반도체 패키지 영역(12)의 중앙면은 칩탑재영역(19)으로 형성되는 바, 이 칩탑재영역(19)은 관통된 형태의 천공홀로서, 이 천공홀에는 양면테이프와 같은 접착수단(30)이 부착되어진다.In addition, the center surface of each semiconductor package region 12 is formed as a chip mounting region 19, the chip mounting region 19 is a through-hole punched hole, the adhesive hole such as double-sided tape Means 30 are attached.
또한, 상기 칩탑재영역(19)의 횡방향 두 개의 변에서 바로 인접된 곳에는 와이어 본딩용 전도성패턴(31)이 배열된다.In addition, a wire bonding conductive pattern 31 is arranged at a portion immediately adjacent to two lateral sides of the chip mounting region 19.
한편, 상기 와이어 본딩용 전도성패턴(31)과 상기 종방향의 슬롯홀(14) 사이의 영역에 걸쳐 전도성의 솔더볼(36)이 융착되는 다수개의 인출단자 부착용랜드(16)가 2열의 배열을 이루며 소정의 간격으로 형성된다.Meanwhile, a plurality of lead terminal attachment lands 16 in which conductive solder balls 36 are fused over an area between the wire bonding conductive pattern 31 and the longitudinal slot hole 14 form an array of two rows. It is formed at predetermined intervals.
특히, 첨부한 도 1에서 은선으로 나타낸 바와 같이, 상기 몰딩수지 흐름용 게이트면(18)과 다수의 인출단자 부착용 랜드(16)가 형성된 영역의 안쪽영역은 상기 칩탑재영역(19)과 와이어 본딩용 전도성패턴(31)을 포함하는 몰딩영역(20)으로 형성된다.In particular, as shown by the hidden line in FIG. 1, an inner region of the region where the molding resin flow gate surface 18 and the plurality of lead terminal attaching lands 16 are formed is wire bonded with the chip mounting region 19. It is formed as a molding region 20 including a conductive pattern 31 for.
여기서, 상기와 같은 구조로 이루어진 본 발명의 반도체 패키지 제조용 부재를 이용하여 반도체 패키지를 제조하는 방법에 대하여 설명하면 다음과 같다.Herein, a method of manufacturing a semiconductor package using the semiconductor package manufacturing member of the present invention having the above structure will be described.
우선, 상기 각각의 반도체 패키지 영역(12)의 칩탑재영역(19), 즉 천공홀에 부착되어 있는 양면테이프와 같은 접착수단(30)에 반도체 칩(28)을 부착하는 단계와; 상기 반도체 칩(28)의 본딩패드와 상기 와이어 본딩용 전도성패턴(31)간을 와이어(32)로 본딩하는 단계를 진행시키게 된다.First, attaching the semiconductor chip 28 to the chip mounting region 19 of each semiconductor package region 12, i.e., adhesive means 30 such as a double-sided tape attached to the perforation hole; Bonding the bonding pad of the semiconductor chip 28 and the conductive pattern 31 for wire bonding with the wire 32 is performed.
여기서, 다음의 몰딩공정을 위하여 상기 부재(10a)의 런너면(21)이 형성된 방향으로 배열되어 있는 다수개의 반도체 패키지 영역(12)을 하나의 몰딩 열로 설정하게 된다.Here, the plurality of semiconductor package regions 12 arranged in the direction in which the runner surface 21 of the member 10a is formed for the next molding process is set as one molding row.
따라서, 상기 몰딩 열로 설정된 다수개의 반도체 패키지 영역(12)내의 몰딩영역(20)을 몰딩다이(40)를 사용하여 한꺼번에 클램핑되도록 하는 바, 상기 몰딩다이(40)의 하형(44)에 상기 부재(10a)를 안착시키고, 상형(42)을 클램핑시키게 되면, 상기 상형(42)에 형성된 각 캐비티(46)와, 상기 반도체 칩(28)과 와이어(32)와 와이어 본딩용 전도성패턴(31)을 포함하는 부재(10a)의 각 몰딩영역(20)이 상하로 일치되고, 상기 상형(42)의 각 캐비티(46) 사이에 형성된 런너공간(48)이 상기 부재(10a)의 몰딩수지 흐름용 런너면(21)과 상하로 일치되어진다.Therefore, the molding regions 20 in the plurality of semiconductor package regions 12 set as the molding columns are clamped at one time by using the molding die 40. When 10a) is seated and the upper die 42 is clamped, the cavities 46 formed on the upper die 42, the semiconductor chip 28, the wire 32, and the conductive pattern 31 for wire bonding are removed. Each molding region 20 of the member 10a including the upper and lower sides coincides with each other, and a runner space 48 formed between the cavities 46 of the upper mold 42 is a runner for molding resin flow of the member 10a. It coincides with the surface 21 up and down.
이에, 상기 몰딩다이(40)의 수지공급구를 통하여 수지(34)를 측방향에서 공급하게 되면, 수지(34)가 상기 각 반도체 패키지 영역(12)의 몰딩수지 흐름용 런너면(21)과 게이트면(18)를 따라 각 몰딩영역(20)에 순차적으로 흘러서 채워지게 된다.Accordingly, when the resin 34 is supplied laterally through the resin supply hole of the molding die 40, the resin 34 may be formed with the runner surface 21 for molding resin flow in each of the semiconductor package regions 12. The molding regions 20 are sequentially flowed and filled along the gate surface 18.
좀 더 상세하게는, 상기 수지(34)가 몰딩다이(40)의 상형(42)에 형성된 첫번째 캐비티(46)에 채워져 첫번째 반도체 패키지 영역(12)내의 몰딩영역(20)을 몰딩하게 되고, 연이어서 수지(34)는 상기 런너면(21)과 게이트면(18)를 타고 계속 흘러서 두번째 캐비티(46)에 채워지며 그 다음의 반도체 패키지 영역(12)내의 몰딩영역(20)을 몰딩하게 된다.More specifically, the resin 34 is filled in the first cavity 46 formed in the upper die 42 of the molding die 40 to mold the molding region 20 in the first semiconductor package region 12. The resin 34 then continues to flow through the runner face 21 and the gate face 18 to fill the second cavity 46 and to mold the molding region 20 in the next semiconductor package region 12.
이와 같이, 수지(34)는 상형(42)의 각 캐비티(46)로 계속 흐르면서 각 반도체 패키지 영역(12)내의 몰딩영역(20)을 순차적으로 한꺼번에 몰딩하게 된다.In this way, the resin 34 continues to flow into each cavity 46 of the upper mold 42 to sequentially mold the molding regions 20 in each semiconductor package region 12 at once.
그에따라, 상기 각 몰딩영역(20)내의 반도체 칩(28)과, 와이어(32)와, 와이어 본딩용 전도성패턴(31)이 수지(34)로 용이하게 몰딩되어진다.Accordingly, the semiconductor chip 28, the wire 32, and the wire bonding conductive pattern 31 in each of the molding regions 20 are easily molded with the resin 34.
다음 단계로서, 상기 부재(10a)의 인출단자 부착용 랜드(16)에 전도성의 솔더볼(36)과 같은 인출단자를 융착하는 단계를 진행시킨다.As a next step, the step of fusing a lead terminal, such as a conductive solder ball 36, to the lead terminal attachment land 16 of the member 10a.
마직막으로, 상기 부재(10a)의 각 몰딩수지 흐름용 게이트면(18)를 펀칭수단으로 펀칭을 하여, 낱개 단위의 반도체 패키지(100)로 싱귤레이션하는 단계를 진행시킴으로서, 도 4a,4b에 도시한 바와 같은 구조의 반도체 패키지(100)로 제조된다.Finally, each of the molding resin flow gate surfaces 18 of the member 10a is punched by a punching means to perform singulation into individual semiconductor packages 100, as shown in FIGS. 4A and 4B. It is made of a semiconductor package 100 having a structure as described above.
상기 싱귤레이션 단계를 보다 상세하게 설명하면 다음과 같다.The singulation step will be described in more detail as follows.
상기 부재(10a)의 슬롯홀(14)이 형성되지 않은 영역은 상술한 바와 같이 몰딩수지의 게이트면(18)으로 형성되는 동시에 펀칭영역으로도 형성되어 있는 바, 몰딩공정후 몰드플러시가 남게 되지만, 펀칭수단에 의한 펀칭으로 용이하게 제거되어진다.The region in which the slot hole 14 of the member 10a is not formed is formed as the gate surface 18 of the molding resin as described above and is also formed as a punching region, so that the mold flush remains after the molding process. It is easily removed by punching by punching means.
이에, 상기 펀칭영역을 한꺼번에 펀칭으로 제거해줌으로써, 각 반도체 패키지 영역(12)은 낱개의 반도체 패키지(100)로 한꺼번에 싱귤레이션된다.Thus, by removing the punching regions at once by punching, each semiconductor package region 12 is singulated into a single semiconductor package 100 at a time.
그에따라, 상기 펀칭에 의한 싱귤레이션 공정시, 작업시간을 대비하여 한 번에 다수의 반도체 패키지를 한꺼번에 싱귤레이션함에 따라, 시간당 단위 생산성을 크게 향상시킬 수 있게 된다.Accordingly, in the singulation process by the punching, as the singulation of a plurality of semiconductor packages at once in preparation for the working time, it is possible to greatly improve the unit productivity per hour.
이상에서 본 바와 같이, 본 발명에 따른 반도체 패키지 제조용 부재 및 그 제조방법에 의하면, 반도체 패키지 영역이 매트릭스 배열로 형성되어 있는 부재에 있어서, 각각의 반도체 패키지 영역의 두 변에 슬롯홀을 형성하고, 나머지 두 변의 양쪽 일부분에도 슬롯홀을 연장시켜 형성함으로써, 각각의 반도체 패키지 영역이 펀칭수단에 의하여 낱개의 반도체 패키지로 한꺼번에 펀칭되어, 시간당 단위 생산성을 크게 향상시킬 수 있는 장점이 있다.As described above, according to the member for manufacturing a semiconductor package and the method for manufacturing the same according to the present invention, in a member in which the semiconductor package regions are formed in a matrix arrangement, slot holes are formed in two sides of each semiconductor package region, By forming slot holes in both portions of the remaining two sides, the respective semiconductor package regions are punched together into a single semiconductor package by the punching means, thereby improving the unit productivity per hour.
아울러, 종래에 비용이 많이 드는 블레이드에 의한 싱귤레이션 공정을 배제할 수 있어 비용을 절감시킬 수 있게 된다.In addition, it is possible to eliminate the singulation process by the conventionally expensive blades it is possible to reduce the cost.
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