KR100344818B1 - 반도체소자및그의제조방법 - Google Patents
반도체소자및그의제조방법 Download PDFInfo
- Publication number
- KR100344818B1 KR100344818B1 KR1019970048550A KR19970048550A KR100344818B1 KR 100344818 B1 KR100344818 B1 KR 100344818B1 KR 1019970048550 A KR1019970048550 A KR 1019970048550A KR 19970048550 A KR19970048550 A KR 19970048550A KR 100344818 B1 KR100344818 B1 KR 100344818B1
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 36
- 125000006850 spacer group Chemical group 0.000 claims abstract description 20
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 7
- 230000010354 integration Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (9)
- 액티브영역의 표면보다 낮게 형성된 필드영역을 가지는 반도체 기판,상기 필드영역의 상부 측면이 드러나도록 소정깊이에 형성된 격리층,상기 액티브영역위에 차례로 형성된 게이트절연막 및 게이트 전극,상기 게이트 전극 양측의 노출된 액티브영역 및 상기 드러난 필드영역의 상부측면내에 형성되는 불순물영역으로 구성됨을 특징으로 하는 반도체 소자.
- 제 1 항에 있어서, 상기 게이트 전극 표면 및 상기 불순물영역상에 형성되는 실리사이드층을 더 포함함을 특징으로 하는 반도체 소자.
- 액티브영역과 필드영역을 정의하여 필드영역의 반도체 기판에 기판과 동일한 높이로 격리층을 형성하는 공정과,상기 액티브영역의 반도체 기판에 게이트절연막과 게이트 전극을 차례로 형성하는 공정과,상기 게이트 전극 측면에 측벽스페이서를 형성함과 동시에 격리층을 소정깊이로 식각하는 공정과,상기 게이트 전극 양측의 반도체 기판 표면에 격리층까지 확장되도록 불순물영역을 형성하는 공정을 포함함을 특징으로 하는 반도체 소자의 제조방법.
- 제 3 항에 있어서, 상기 격리층은 필드영역에 트랜치를 형성하는 공정과, 상기 트랜치내에 절연막을 증착하는 공정을 통하여 형성하는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 3 항에 있어서, 상기 게이트 전극 표면 및 상기 불순물영역상에 실리사이드층을 형성하는 것을 더 포함함을 특징으로 반도체 소자의 제조방법.
- 제 3 항에 있어서, 상기 불순물영역은 틸트이온 주입하여 형성함을 특징으로 하는 반도체 소자의 제조방법.
- 액티브영역과 필드영역을 정의하여 필드영역의 반도체기판에 기판과 동일한 높이로 격리층을 형성하는 공정과,상기 액티브영역의 반도체 기판에 게이트절연막과 게이트전극을 차례로 형성하는 공정과,상기 격리층을 소정깊이로 식각하여 상기 필드영역의 상부 측면이 드러나도록 하는 공정과,상기 게이트 전극의 양측의 반도체기판 표면 및 상기 드러난 필드영역의 상부 측면에 불순물영역을 형성하는 공정을 포함함을 특징으로 하는 반도체 소자의 제조방법.
- 제 7 항에 있어서, 상기 불순물영역은 틸트이온 주입하여 형성함을 특징으로 하는 반도체 소자의 제조방법.
- 제 7 항에 있어서, 상기 불순물영역상에 실리사이드층을 형성하는 것을 더 포함함을 특징으로 반도체 소자의 제조방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970048550A KR100344818B1 (ko) | 1997-09-24 | 1997-09-24 | 반도체소자및그의제조방법 |
US09/006,479 US6017801A (en) | 1997-09-24 | 1998-01-13 | Method for fabricating field effect transistor |
JP10034553A JPH11111981A (ja) | 1997-09-24 | 1998-02-17 | 半導体デバイス及びその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970048550A KR100344818B1 (ko) | 1997-09-24 | 1997-09-24 | 반도체소자및그의제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR19990026437A KR19990026437A (ko) | 1999-04-15 |
KR100344818B1 true KR100344818B1 (ko) | 2002-11-18 |
Family
ID=19521609
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970048550A KR100344818B1 (ko) | 1997-09-24 | 1997-09-24 | 반도체소자및그의제조방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6017801A (ko) |
JP (1) | JPH11111981A (ko) |
KR (1) | KR100344818B1 (ko) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3415459B2 (ja) * | 1998-12-07 | 2003-06-09 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6133105A (en) * | 1999-04-27 | 2000-10-17 | United Microelectronics Corp. | Method of manufacturing borderless contact hole including a silicide layer on source/drain and sidewall of trench isolation structure |
DE10052208C2 (de) * | 2000-10-20 | 2002-11-28 | Advanced Micro Devices Inc | Verfahren zur Herstellung eines Feldeffekttransistors mittels einer Justiertechnologie auf der Grundlage von Seitenwandabstandselementen |
US6580122B1 (en) * | 2001-03-20 | 2003-06-17 | Advanced Micro Devices, Inc. | Transistor device having an enhanced width dimension and a method of making same |
KR100414735B1 (ko) * | 2001-12-10 | 2004-01-13 | 주식회사 하이닉스반도체 | 반도체소자 및 그 형성 방법 |
US6812103B2 (en) * | 2002-06-20 | 2004-11-02 | Micron Technology, Inc. | Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects |
KR100466207B1 (ko) * | 2002-07-04 | 2005-01-13 | 매그나칩 반도체 유한회사 | 반도체 소자의 제조 방법 |
JP4470398B2 (ja) * | 2003-06-23 | 2010-06-02 | Tdk株式会社 | 電界効果トランジスタ |
US7361973B2 (en) * | 2004-05-21 | 2008-04-22 | International Business Machines Corporation | Embedded stressed nitride liners for CMOS performance improvement |
US7186622B2 (en) * | 2004-07-15 | 2007-03-06 | Infineon Technologies Ag | Formation of active area using semiconductor growth process without STI integration |
US7358571B2 (en) * | 2004-10-20 | 2008-04-15 | Taiwan Semiconductor Manufacturing Company | Isolation spacer for thin SOI devices |
US7491614B2 (en) * | 2005-01-13 | 2009-02-17 | International Business Machines Corporation | Methods for forming channel stop for deep trench isolation prior to deep trench etch |
US7298009B2 (en) * | 2005-02-01 | 2007-11-20 | Infineon Technologies Ag | Semiconductor method and device with mixed orientation substrate |
KR100691009B1 (ko) * | 2005-05-27 | 2007-03-09 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
US7253481B2 (en) * | 2005-07-14 | 2007-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance MOS device with graded silicide |
US8530355B2 (en) | 2005-12-23 | 2013-09-10 | Infineon Technologies Ag | Mixed orientation semiconductor device and method |
US20070190795A1 (en) * | 2006-02-13 | 2007-08-16 | Haoren Zhuang | Method for fabricating a semiconductor device with a high-K dielectric |
US7442619B2 (en) * | 2006-05-18 | 2008-10-28 | International Business Machines Corporation | Method of forming substantially L-shaped silicide contact for a semiconductor device |
US7569896B2 (en) * | 2006-05-22 | 2009-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistors with stressed channels |
US7364957B2 (en) * | 2006-07-20 | 2008-04-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for semiconductor device with improved source/drain junctions |
US20080150026A1 (en) * | 2006-12-26 | 2008-06-26 | International Business Machines Corporation | Metal-oxide-semiconductor field effect transistor with an asymmetric silicide |
US20100032759A1 (en) * | 2008-08-11 | 2010-02-11 | International Business Machines Corporation | self-aligned soi schottky body tie employing sidewall silicidation |
US9246004B2 (en) * | 2011-11-15 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structures of semiconductor devices |
US8664072B2 (en) * | 2012-05-30 | 2014-03-04 | Globalfoundries Inc. | Source and drain architecture in an active region of a P-channel transistor by tilted implantation |
US9177968B1 (en) | 2014-09-19 | 2015-11-03 | Silanna Semiconductor U.S.A., Inc. | Schottky clamped radio frequency switch |
CN111952367B (zh) * | 2019-05-15 | 2024-06-07 | 长鑫存储技术有限公司 | 半导体结构及其形成方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01143357A (ja) * | 1987-11-30 | 1989-06-05 | Hitachi Ltd | 半導体装置およびその製法 |
Family Cites Families (8)
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US4622735A (en) * | 1980-12-12 | 1986-11-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing a semiconductor device utilizing self-aligned silicide regions |
JPS58175846A (ja) * | 1982-04-08 | 1983-10-15 | Toshiba Corp | 半導体装置の製造方法 |
KR900007686B1 (ko) * | 1986-10-08 | 1990-10-18 | 후지쓰 가부시끼가이샤 | 선택적으로 산화된 실리콘 기판상에 에피택셜 실리콘층과 다결정 실리콘층을 동시에 성장시키는 기상 증착방법 |
US4716128A (en) * | 1986-12-10 | 1987-12-29 | General Motors Corporation | Method of fabricating silicon-on-insulator like devices |
US4786955A (en) * | 1987-02-24 | 1988-11-22 | General Electric Company | Semiconductor device with source and drain depth extenders and a method of making the same |
JP3017860B2 (ja) * | 1991-10-01 | 2000-03-13 | 株式会社東芝 | 半導体基体およびその製造方法とその半導体基体を用いた半導体装置 |
US5849621A (en) * | 1996-06-19 | 1998-12-15 | Advanced Micro Devices, Inc. | Method and structure for isolating semiconductor devices after transistor formation |
US5824586A (en) * | 1996-10-23 | 1998-10-20 | Advanced Micro Devices, Inc. | Method of manufacturing a raised source/drain MOSFET |
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1997
- 1997-09-24 KR KR1019970048550A patent/KR100344818B1/ko not_active IP Right Cessation
-
1998
- 1998-01-13 US US09/006,479 patent/US6017801A/en not_active Expired - Lifetime
- 1998-02-17 JP JP10034553A patent/JPH11111981A/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01143357A (ja) * | 1987-11-30 | 1989-06-05 | Hitachi Ltd | 半導体装置およびその製法 |
Also Published As
Publication number | Publication date |
---|---|
US6017801A (en) | 2000-01-25 |
JPH11111981A (ja) | 1999-04-23 |
KR19990026437A (ko) | 1999-04-15 |
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