KR0170913B1 - Contact forming method of semiconductor device - Google Patents
Contact forming method of semiconductor device Download PDFInfo
- Publication number
- KR0170913B1 KR0170913B1 KR1019950003906A KR19950003906A KR0170913B1 KR 0170913 B1 KR0170913 B1 KR 0170913B1 KR 1019950003906 A KR1019950003906 A KR 1019950003906A KR 19950003906 A KR19950003906 A KR 19950003906A KR 0170913 B1 KR0170913 B1 KR 0170913B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- forming
- oxide film
- semiconductor device
- contact
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 콘택 형성방법에 관한 것으로, 반도체기판 상부에 제1절연막을 형성하고 그 상부에 도전배선을 형성한 다음, 상기 도전배선의 표면에 제2절연막을 형성하고 전체표면을 평탄화시키는 제3절연막을 형성한 다음, 콘택마스크를 이용한 식각공정으로 제1콘택홀을 형성하고 전체표면을 습식방법으로 일정두께 식각한 다음, 마스크를 이용한 식각공정으로 확산방지막, 금속막 및 반사방지막을 순차적으로 형성함으로써 반도체소자의 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, wherein a first insulating film is formed on a semiconductor substrate and a conductive wiring is formed on the semiconductor substrate, and a second insulating film is formed on the surface of the conductive wiring and the entire surface is planarized. After the third insulating film is formed, the first contact hole is formed by an etching process using a contact mask, and the entire surface is etched by a wet method using a wet method, and then the diffusion barrier, the metal film, and the antireflection film are sequentially formed by an etching process using a mask. It is a technology that improves the reliability of the semiconductor device by forming the semiconductor device and enables high integration of the semiconductor device.
Description
제1도(a) 내지 제1도(g)는 본 발명의 제1실시예에 따른 반도체소자의 콘택 형성공정을 도시한 단면도.1A to 1G are cross-sectional views showing a contact forming process of a semiconductor device according to a first embodiment of the present invention.
제2도는 본 발명의 제2실시예에 따른 반도체소자의 콘택 형성공정을 도시한 단면도.2 is a cross-sectional view showing a contact forming process of a semiconductor device according to a second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체기판 13 : 불순물 확산영역11: semiconductor substrate 13: impurity diffusion region
15 : 제1산화막 17 : 다결정실리콘막15: first oxide film 17: polycrystalline silicon film
19 : 실리콘질화막 21 : 제2산화막19 silicon nitride film 21 second oxide film
23 : 감광막패턴 25 : 제1콘택홀23: photoresist pattern 25: the first contact hole
27 : 제2콘택홀 29,35 : 티타늄/티타늄질화막27: second contact hole 29, 35: titanium / titanium nitride film
31,37 : 알루미늄합금 33,39 : 티타늄31,37: Aluminum alloy 33,39: Titanium
본 발명은 반도체소자의 콘택 형성방법에 관한 것으로, 특히 반도체소자가 고집적화됨에따라 콘택홀의 크기가 작아져 한계점에 도달한 노광기술을 극복하기 위하여 콘택홀 형성공정 이전에 형성되는 도전배선의 표면에 절연막을 형성하고 그 후에 콘택홀을 확장시켜 콘택물질로 사용되는 금속물질의 단차피복비를 크게 개선할 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device. In particular, as the semiconductor device is highly integrated, an insulating film is formed on the surface of the conductive wiring formed before the contact hole forming process to overcome the exposure technology which reaches the limit due to the small contact hole size. The present invention relates to a technology capable of greatly improving the step coverage ratio of a metal material used as a contact material by forming a contact hole and then expanding the contact hole.
반도체소자가 고집적화됨에따라 작아지는 콘택홀의 크기에 충족하는 노광기술이 부족하여 미세콘택홀 형성이 어렵다. 그리고, 상기 콘택홀이 형성되더라도 단차피복비가 좋지못하여 콘택형성이 어려웠다.As the semiconductor devices are highly integrated, there is a lack of exposure technology that satisfies the size of the contact hole, which is small. In addition, even if the contact hole is formed, it is difficult to form a contact because the step coverage ratio is not good.
이를 위하여, 종래기술에서는 상기 콘택홀의 상부를 습식방법으로 식각하여 언더컷 ( under cut ) 을 형성함으로써 단차피복비를 증가시켰다.To this end, in the prior art, the upper portion of the contact hole was etched by a wet method to form an under cut, thereby increasing the step coverage ratio.
그러나, 콘택홀을 형성하기위한 상기 습식식각공정시 언더컷에 의하여 도전배선을 손상시키거나 노출시킬 수 있다. 그로인하여, 금속물질을 이용한 콘택공정시 단락이 발생함으로써 반도체소자의 신뢰성을 저하시키고 반도체소자의 고집적화를 어렵게하는 문제점이 있다.However, the conductive wiring may be damaged or exposed by the undercut during the wet etching process for forming the contact hole. As a result, a short circuit occurs during a contact process using a metal material, thereby lowering the reliability of the semiconductor device and making it difficult to integrate the semiconductor device.
따라서, 본 발명은 종래기술의 문제점을 해결하기위하여, 반도체기판 상부에 형성된 도전배선에 절연막을 형성하고 후공정에서 습식방법으로 콘택홀의 상부를 넓게 형성하여 콘택공정시의 단차피복비를 증가시킴으로써 반도체소자의 특성을 향상시켜 반도체소자의 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 반도체소자의 콘택 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the problems of the prior art, the semiconductor device is formed by forming an insulating film on the conductive wiring formed on the semiconductor substrate and forming the upper portion of the contact hole by a wet method in a later process to increase the step coverage ratio during the contact process. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a contact for a semiconductor device by improving the characteristics of the semiconductor device, thereby improving reliability of the semiconductor device and enabling high integration of the semiconductor device.
이상의 목적을 달성하기위한 본 발명인 반도체소자의 콘택 형성방법의 특징은, 반도체기판에 불순물 확산영역을 형성하는 공정과, 상기 반도체기판에 제1절연막을 형성하는 공정과, 상기 제1절연막 상부에 도전배선을 형성하는 공정과, 전체표면상부에 제2절연막을 형성하는 공정과, 상기 도전배선간에 형성된 제2절연막의 두께만큼 전면식각함으로써 상기 도전배선의 표면에 제2절연막을 형성하는 공정과, 전체표면상부에 평탄화된 제3절연막을 형성하는 공정과, 콘택마스크를 이용하여 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로하여 상기 제3절연막을 일정두께 습식방법으로 등방성식각하는 공정과, 상기 감광막패턴을 마스크로하여 상기 제3절연막과 제1절연막을 순차적으로 건식식각하는 공정과, 상기 감광막패턴을 제거하는 공정과, 전체표면을 습식방법으로 일정두께 식각하는 공정과, 전체표면상부에 확산방지막과 금속막 그리고 반사방지막을 순차적으로 형성하는 공정과, 금속배선을 형성하기위한 마스크를 이용하여 상기 반사방지막, 금속막 및 확산방지막을 순차적으로 식각함으로써 금속배선을 형성하는 공정을 포함하는데 있다.The contact forming method of the semiconductor device of the present invention for achieving the above object is a step of forming an impurity diffusion region in the semiconductor substrate, a step of forming a first insulating film on the semiconductor substrate, and a conductive on the first insulating film Forming a wiring, forming a second insulating film on the entire surface, forming a second insulating film on the surface of the conductive wiring by etching the entire surface by the thickness of the second insulating film formed between the conductive wirings; Forming a planarized third insulating film on the surface, forming a photosensitive film pattern using a contact mask, isotropically etching the third insulating film by a constant thickness wet method using the photosensitive film pattern as a mask; Sequentially etching the third insulating film and the first insulating film using the photosensitive film pattern as a mask, and removing the photosensitive film pattern. A step of etching the entire surface by a wet method, a step of sequentially forming a diffusion barrier film, a metal film and an antireflection film on the entire surface, and a mask for forming a metal wiring. It includes a step of forming a metal wiring by sequentially etching the film and the diffusion barrier film.
또한, 상기 제1절연막과 제3절연막은 플로우가 잘되는 절연물질로서, 보론이나 인이 함유된 것과, 상기 제2절연막은 상기 도전배선의 상부 및 측면이 상기 도전배선과 도전배선보다 두껍게 형성되는 것과, 상기 제2절연막은 실리콘질화막으로 형성되는 것과, 상기 건식식각은 플라즈마가 이용되는 것과, 상기 확산방지막은 티타늄과 티타늄질화막의 적층구조로 형성되는 것과, 상기 금속막은 알루미늄합금이 사용되는 것과, 상기 알루미늄합금은 실온 내지 250 ℃ 의 온도에서 한번의 증착공정으로 형성되는 것과, 상기 알루미늄합금은 두번의 증착공정으로 형성되되, 상기 첫번째 증착공정은 실온 내지 250 ℃ 온도의 제1챔버에서 전체증착두께의 이할 내지 사할을 형성하고, 상기 두번째 증착공정은 450 내지 650 ℃ 온도의 제2챔버에서 전체증착두께의 팔할 내지 육할을 형성하는 것과, 상기 반사방지막은 상기 금속막보다 반사율이 적은 물질로 형성되는 것과, 상기 반사방지막은 티타늄, 티타늄질화막 또는 실리콘으로 형성되는 것과, 상기 제1절연막과 제3절연막은 플로우가 잘되는 절연물질로서, 보론이나 인이 함유된 것이다.In addition, the first insulating film and the third insulating film are well-flowing insulating materials, containing boron or phosphorus, and the second insulating film having a thicker upper and side surfaces of the conductive wiring than the conductive wiring and the conductive wiring. The second insulating layer is formed of a silicon nitride film, the dry etching is plasma is used, the diffusion barrier is formed of a laminated structure of titanium and titanium nitride film, the metal film is an aluminum alloy is used, The aluminum alloy is formed by one deposition process at a temperature of room temperature to 250 ℃, the aluminum alloy is formed by two deposition processes, the first deposition process is the total deposition thickness in the first chamber of the room temperature to 250 ℃ temperature Forming a second to four fourths, and the second deposition process is the arm of the total deposition thickness in the second chamber at a temperature of 450 to 650 ℃ To sixth percentile, the antireflection film is formed of a material having a lower reflectance than the metal film, the antireflection film is formed of titanium, titanium nitride film, or silicon, and the first insulating film and the third insulating film have a flow Good insulation material, containing boron or phosphorus.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도(a) 내지 제1도(g)는 본 발명의 제1실시예에 따른 반도체소자의 콘택 형성공정을 도시한 단면도이다.1A to 1G are cross-sectional views illustrating a process for forming a contact of a semiconductor device according to a first embodiment of the present invention.
제1도(a)를 참조하면, 반도체기판(11)의 예정된 부분에 불순물 접합영역(13)을 형성한다. 그리고, 상기 반도체기판(11) 상부에 제1산화막(15)을 형성한다. 그리고, 상기 제1산화막(15) 상부에 다결정실리콘막(17)을 일정두께 형성한다. 이때, 상기 다결정실리콘막(17)은 1000 내지 2000 Å 으로 형성된 것이다. 그 다음에, 비트라인 마스크(도시안됨)를 이용한 사진식각공정으로 상기 다결정실리콘막(17)을 패턴닝하여 다결정실리콘막(17)패턴, 즉 비트라인을 형성한다.Referring to FIG. 1A, an impurity junction region 13 is formed in a predetermined portion of the semiconductor substrate 11. A first oxide film 15 is formed on the semiconductor substrate 11. Then, a polysilicon film 17 is formed on the first oxide film 15 at a predetermined thickness. At this time, the polysilicon film 17 is formed to 1000 to 2000 kPa. Next, the polysilicon layer 17 is patterned by a photolithography process using a bit line mask (not shown) to form a polysilicon layer 17 pattern, that is, a bit line.
제1도(b)를 참조하면, 전체표면상부에 실리콘질화막(19)을 일정두께 증착한다. 이때, 상기 실리콘질화막(19)은 350 내지 450 ℃ 의 온도에서 플라즈마증착방법으로 증착된 것이다. 여기서, 상기 실리콘질화막(19)은 상기 다결정실리콘막(17)패턴들 사이의 제1산화막(15) 상부가 상기 다결정실리콘막(17)패턴 상부보다 얇게 형성된다.Referring to FIG. 1 (b), a silicon nitride film 19 is deposited to a predetermined thickness on the entire surface. At this time, the silicon nitride film 19 is deposited by a plasma deposition method at a temperature of 350 to 450 ℃. In the silicon nitride layer 19, an upper portion of the first oxide layer 15 between the polysilicon layer 17 patterns may be formed thinner than an upper portion of the polysilicon layer 17 pattern.
제1도(c)를 참조하면, 전면식각공정으로 상기 다결정실리콘막(17)패턴과 다결정실리콘막(17)패턴 사이의 제1산화막(15) 상부에 형성된 실리콘질화막(19) 두께만큼 식각한다. 그로인하여, 상기 다결정실리콘막(17)패턴의 표면에만 상기 실리콘질화막(19)이 남게된다.Referring to FIG. 1C, etching is performed as much as the thickness of the silicon nitride layer 19 formed on the first oxide layer 15 between the polysilicon layer 17 pattern and the polysilicon layer 17 pattern by a front surface etching process. . Thus, the silicon nitride film 19 remains only on the surface of the polysilicon film 17 pattern.
제1도(d)를 참조하면, 전체표면상부를 평탄화시키는 제2산화막(21)을 형성한다. 이때, 상기 제2산화막(21)은 불순물이 함유되지않은 산화막을 사용하거나 보론이나 인 등의 불순물이 포함된 산화막으로 형성한다. 그 다음에, 상기 제2산화막(21) 상부에 감광막패턴(23)을 형성한다. 이때, 상기 감광막패턴(23)은 콘택마스크를 이용한 사진공정으로 형성된 것이다.Referring to FIG. 1 (d), a second oxide film 21 is formed to planarize the entire upper surface. In this case, the second oxide film 21 is formed of an oxide film containing no impurities or an oxide film containing impurities such as boron or phosphorus. Next, a photosensitive film pattern 23 is formed on the second oxide film 21. In this case, the photoresist pattern 23 is formed by a photo process using a contact mask.
제1도(e)를 참조하면, 상기 감광막패턴(23)을 마스크로하여 상기 제2산화막(21)을 일정두께 습식방법으로 등방성식각한다. 그로인하여, 감광막패턴(23)의 하부에 언더컷이 형성된다. 그 다음에, 상기 감광막패턴(23)을 마스크로하여 상기 제2산화막(21)과 제1산화막(15)을 순차적으로 건식식각함으로써 상기 반도체기판(11)의 예정된 부분을 노출시키는 제1콘택홀(25)을 형성한다.Referring to FIG. 1E, the second oxide film 21 is isotropically etched by a predetermined thickness wet method using the photoresist pattern 23 as a mask. As a result, an undercut is formed under the photosensitive film pattern 23. Next, the first contact hole exposing a predetermined portion of the semiconductor substrate 11 by sequentially dry etching the second oxide film 21 and the first oxide film 15 using the photoresist pattern 23 as a mask. To form 25.
제1도(f)를 참조하면, 표면에 노출되는 제1,2산화막(15,21)을 습식방법으로 일정두께 식각하여 상기 제1콘택홀(25)이 확장된 제2콘택홀(27)을 형성한다.Referring to FIG. 1 (f), the first contact hole 25 is extended to the second contact hole 27 by etching the first and second oxide films 15 and 21 exposed on the surface by a wet method. To form.
제1도(g)를 참도하면, 상기 제1도(f)의 공정후에 티타늄/티타늄질화막(29)의 적층구조로 증착한다. 이때, 상기 티타늄/티타늄질화막(29)의 적층구조는 확산방지용으로 사용된다. 그 다음에, 전체표면상부에 알루미늄합금(31)을 형성한다. 이때, 상기 알루미늄합금(31)은 실온 내지 250℃ 에서 한번의 증착공정으로 형성한 것이다. 그 후에, 상기 알루미늄합금(29) 상부에 티타늄막(33)을 형성한다. 이때, 상기 티타늄막(33)은 반사방지막으로서, 상기 알루미늄합금(31)의 높은 반사율에의한 난반사를 방지하기위한 것이다. 그리고, 상기 반사방지막은 티타늄텅스텐이나 실리콘과 같이 반사율이 적은 물질을 형성할 수도 있다.Referring to FIG. 1 (g), after the process of FIG. 1 (f), the titanium / titanium nitride film 29 is deposited. In this case, the laminated structure of the titanium / titanium nitride layer 29 is used for diffusion prevention. Then, an aluminum alloy 31 is formed on the entire surface. At this time, the aluminum alloy 31 is formed by one deposition process at room temperature to 250 ℃. After that, a titanium film 33 is formed on the aluminum alloy 29. At this time, the titanium film 33 is an anti-reflection film, to prevent diffuse reflection due to the high reflectance of the aluminum alloy 31. In addition, the anti-reflection film may form a material having a low reflectance such as titanium tungsten or silicon.
3후공정에서, 마스크를 이용한 식각공정으로 상기 티타늄막(33)과 알루미늄합금(31) 그리고 티타늄/티타늄질화막(29)을 식각함으로써 확장된 제2콘택홀(27)을 통하여 상기 반도체기판(11)의 불순물 접합영역(13)에 콘택된 금속배선을 형성한다.In the third process, the semiconductor substrate 11 is formed through the second contact hole 27 extended by etching the titanium film 33, the aluminum alloy 31, and the titanium / titanium nitride film 29 by an etching process using a mask. A metal wiring contacted to the impurity junction region 13 of the "
제2도는 본 발명의 제2실시예에 따른 반도체소자의 콘택 형성공정을 도시한 단면도이다.2 is a cross-sectional view illustrating a process for forming a contact of a semiconductor device according to a second exemplary embodiment of the present invention.
제2도를 참조하면, 상기 제1실시예의 제1도(f)의 공정후에 전체표면상부에 티타늄/티타늄질화막(35)의 적층구조를 형성한다. 그리고, 상기 티타늄/티타늄질화막(35)의 적층구조 상부에 알루미늄합금(37)을 이단계증착방법으로 형성한다.Referring to FIG. 2, after the process of FIG. 1 (f) of the first embodiment, a laminated structure of the titanium / titanium nitride film 35 is formed on the entire surface. In addition, the aluminum alloy 37 is formed on the multilayer structure of the titanium / titanium nitride layer 35 by a two-step deposition method.
여기서, 상기 알루미늄합금(37)은 실온 내지 250℃ 온도의 제1챔버에서 전체두께의 이할 내지 사할을 증착한다. 그리고, 상기 450 내지 650℃ 온도의 제2챔버에서 전체두께의 팔할 내지 육할을 증착한다.Here, the aluminum alloy 37 deposits less than or equal to the total thickness in the first chamber at room temperature to 250 ° C. Then, eighty percent to sixty percent of the total thickness is deposited in the second chamber at the temperature of 450 to 650 ° C.
그 다음에, 상기 알루미늄합금(37) 상부에 티타늄막(39)을 형성한다. 이때, 상기 티타늄막(39)은 반사방지막으로서, 상기 알루미늄합금(37)의 반사율이 높기때문에 광의 난반사를 방지하기위하여 티타늄텅스텐이나 실리콘과 같이 반사율이 적은 물질을 형성한 것이다.Next, a titanium film 39 is formed on the aluminum alloy 37. At this time, since the titanium film 39 is an antireflection film, since the reflectance of the aluminum alloy 37 is high, a material having a low reflectance such as titanium tungsten or silicon is formed to prevent diffuse reflection of light.
후공정에서, 마스크를 이용한 식각공정으로 상기 티타늄막(39)과 알루미늄합금(37) 그리고 티타늄/티타늄질화막(35)을 식각함으로써 확장된 제2콘택홀(27)을 통하여 상기 반도체기판(11)에 콘택된 금속배선을 형성한다.In a later step, the semiconductor substrate 11 is formed through the second contact hole 27 extended by etching the titanium film 39, the aluminum alloy 37, and the titanium / titanium nitride film 35 by an etching process using a mask. A metal wiring contacted is formed.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 콘택 형성방법은, 반도체기판 상부에 형성된 도전배선 손상없이 콘택홀의 크기를 확장시킴으로써 단차피복비를 향상시키고, 후공정에서 금속배선을 형성함으로써 반도체소자의 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, the method for forming a contact of a semiconductor device according to the present invention improves the step coverage ratio by expanding the contact hole size without damaging the conductive wiring formed on the semiconductor substrate, and the reliability of the semiconductor device by forming the metal wiring in a later step. And improve the integration of semiconductor devices.
Claims (14)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950003906A KR0170913B1 (en) | 1995-02-27 | 1995-02-27 | Contact forming method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950003906A KR0170913B1 (en) | 1995-02-27 | 1995-02-27 | Contact forming method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960032611A KR960032611A (en) | 1996-09-17 |
| KR0170913B1 true KR0170913B1 (en) | 1999-03-30 |
Family
ID=19408883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950003906A KR0170913B1 (en) | 1995-02-27 | 1995-02-27 | Contact forming method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0170913B1 (en) |
-
1995
- 1995-02-27 KR KR1019950003906A patent/KR0170913B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960032611A (en) | 1996-09-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5747383A (en) | Method for forming conductive lines and stacked vias | |
| KR0170913B1 (en) | Contact forming method of semiconductor device | |
| KR101096236B1 (en) | METHOD FOR FABRICATING THIN FILM METAL PATTERN AND METAL LINE USING ArF PHOTO LITHOGRAPHY PROCESS | |
| JPH09129730A (en) | Manufacture of semiconductor device | |
| KR100321141B1 (en) | Method for fabricating semiconductor device | |
| KR100191708B1 (en) | Forming method for metal wiring in semiconductor device | |
| KR20000004332A (en) | Method for forming metal wires of semiconductor devices | |
| KR100191710B1 (en) | Metal wiring method of semiconductor device | |
| KR20040048042A (en) | Method of manufacturing a semiconductor device | |
| KR100205095B1 (en) | Method for forming bit line of semiconductor device | |
| KR950009285B1 (en) | Metalizing method of semiconductor device | |
| KR20010047961A (en) | method to shape line first dual damascene pattern use the oxide mask | |
| KR100289653B1 (en) | Wiring Structure of Semiconductor Device and Formation Method | |
| KR100226755B1 (en) | Interconnection structure and manufacturing method of the same in semiconductor device | |
| KR100265749B1 (en) | Method of fabricating metal line of semiconductor device | |
| KR100296132B1 (en) | Method for forming metal wiring of semiconductor device using large machine | |
| KR100237743B1 (en) | Method for forming metal interconnector in semiconductor device | |
| KR19990055779A (en) | Contact Forming Method of Semiconductor Device | |
| KR20040087045A (en) | Method for fabricating of semiconductor device | |
| KR20040056110A (en) | Method of forming a dual damascene pattern | |
| KR100232224B1 (en) | Method of forming metal interconnector of semiconductor device | |
| KR0148326B1 (en) | Fabrication method of semiconductor device | |
| KR100393970B1 (en) | method for forming metal contact semiconductor device | |
| KR100314741B1 (en) | Method for forming metal line in semiconductor device | |
| KR100447982B1 (en) | Method for forming metal interconnection of semiconductor device using buffer layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050923 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |