KR100296132B1 - Method for forming metal wiring of semiconductor device using large machine - Google Patents

Method for forming metal wiring of semiconductor device using large machine Download PDF

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KR100296132B1
KR100296132B1 KR1019980024710A KR19980024710A KR100296132B1 KR 100296132 B1 KR100296132 B1 KR 100296132B1 KR 1019980024710 A KR1019980024710 A KR 1019980024710A KR 19980024710 A KR19980024710 A KR 19980024710A KR 100296132 B1 KR100296132 B1 KR 100296132B1
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film
metal wiring
insulating film
forming
metal
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KR1019980024710A
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KR20000003468A (en
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여인석
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer

Abstract

본 발명은 감광막 패턴의 무너짐을 방지할 수 있으며, 금속배선의 두께를 보다 정확히 조절할 수 있는 대머신 방법을 이용한 반도체 소자의 금속배선 형성 방법에 관한 것으로, 금속배선 위치에 감광막 패턴을 형성하고, 절연막을 증착하고 절연막을 연마하여 감광막 패턴을 노출시키고, 감광막 패턴을 제거한 다음 금속막을 증착하고 연마하여 금속배선을 형성하는데 그 특징이 있다.The present invention relates to a method for forming a metal wiring of a semiconductor device using a large machine method that can prevent the photosensitive film pattern from collapsing, and to more precisely control the thickness of the metal wiring. Is deposited and polished the insulating film to expose the photoresist pattern, the photoresist pattern is removed, and the metal film is deposited and polished to form the metal wiring.

Description

대머신 방법을 이용한 반도체 소자의 금속배선 형성 방법Method for forming metal wiring of semiconductor device using large machine method

본 발명은 반도체 장치 제조 분야에 관한 것으로, 특히 대머신(damascene) 방법을 이용한 반도체 소자의 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of manufacturing semiconductor devices, and more particularly, to a method of forming metal wirings in semiconductor devices using a damascene method.

반도체 소자의 금속배선은 Al, Cu 등의 금속막 상에 배선의 형상을 정의하는 감광막 패턴을 형성하고, 감광막 패턴을 식각마스크로 금속막을 건식식각하는 일련의 과정을 통하여 형성되는데, 반도체 소자의 집적도가 향상됨에 따라 감광막 패턴의 종횡비(aspect ratio)가 커져 감광막 패턴이 쓰러지거나 건식식각 후 부식(corrosion)의 발생 가능성이 높은 문제점이 있다. 또한, 금속막마다 식각 특성이 상이하기 때문에 새로운 식각 조건을 개발하여야 한다. 그 예로서, Cu막은 통상의 건식식각 조건에서 휘발성이 낮은 화합물을 형성하기 때문에, 화합물을 제거할 수 있는 식각 조건이 개발되어야 한다.The metal wiring of the semiconductor device is formed through a series of processes of forming a photoresist pattern defining a shape of the wiring on a metal film such as Al and Cu, and dry etching the metal film using the photoresist pattern as an etching mask. As the aspect ratio of the photoresist pattern increases, the aspect ratio of the photoresist pattern increases, so that the photoresist pattern collapses or there is a high possibility of occurrence of corrosion after dry etching. In addition, since the etching characteristics are different for each metal film, a new etching condition must be developed. As an example, since the Cu film forms a compound having low volatility under normal dry etching conditions, an etching condition capable of removing the compound must be developed.

전술한 문제점을 해결하기 위한 방법으로 대머신 방법이 이용되고 있다.The alternative machine method is used as a method for solving the above-mentioned problems.

첨부된 도면 도1a 내지 도1c를 참조하여 종래의 대머신 방법에 따른 반도체 소자의 금속배선 형성 방법을 설명한다.1A to 1C, a method of forming metal wirings of a semiconductor device according to a conventional machine method will be described.

먼저, 도1a에 도시한 바와 같이 반도체 기판 또는 층간절연막(10) 상에 절연막(11)을 형성한다.First, as shown in FIG. 1A, an insulating film 11 is formed on a semiconductor substrate or an interlayer insulating film 10.

다음으로, 도1b에 도시한 바와 같이 절연막(11) 상에 금속배선 형성 부분을 노출시키는 감광막 패턴(30)을 형성한 후, 감광막 패턴(30)을 식각마스크로 절연막(11)을 선택적으로 식각하여 금속배선이 형성될 부분의 절연막(11)을 제거한다.Next, as shown in FIG. 1B, after forming the photoresist pattern 30 exposing the metal wiring forming portion on the insulation layer 11, the photoresist pattern 30 is selectively etched with the etching mask. Thus, the insulating film 11 of the portion where the metal wiring is to be formed is removed.

다음으로, 도1c에 도시한 바와 같이 전체 구조 상에 금속막(12)을 증착하고 금속막(12)을 연마하여 절연막(11) 사이의 금속배선 위치에 금속막(12)이 남도록 한다.Next, as shown in FIG. 1C, the metal film 12 is deposited on the entire structure and the metal film 12 is polished so that the metal film 12 remains at the metal wiring position between the insulating films 11.

전술한 바와 같이 이루어지는 종래의 대머신 방법을 이용한 금속배선 형성 방법은, 소자의 집적도에 따라 감광막 패턴의 종횡비가 커지기 때문에 감광막 패턴의 쓰러짐을 근본적으로 해결할 수 없는 문제점이 있다. 또한, 하부 절연막(10)과 상부 절연막(11)의 식각 성질이 유사할 경우에는 식각정지 위치를 정확하게 조절하기가 어려워 금속배선의 두께가 의도한 대로 형성되지 않는 단점이 있다.Since the aspect ratio of the photosensitive film pattern increases according to the degree of integration of the device, the method for forming a metal wiring using the conventional large-machine method has the problem that the collapse of the photosensitive film pattern cannot be fundamentally solved. In addition, when the etching properties of the lower insulating film 10 and the upper insulating film 11 are similar to each other, it is difficult to precisely control the etching stop position, which causes a disadvantage that the thickness of the metal wiring is not formed as intended.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 감광막 패턴의 무너짐을 방지할 수 있으며, 금속배선의 두께를 보다 정확히 조절할 수 있는 대머신 방법을 이용한 반도체 소자의 금속배선 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems can prevent the collapse of the photosensitive film pattern, and to provide a method for forming a metal wiring of the semiconductor device using a large machine method that can more accurately control the thickness of the metal wiring. There is this.

도1a 내지 도1c 종래의 대머신 방법에 따른 반도체 소자의 금속배선 형성 공정 단면도1A to 1C are cross-sectional views of a metal wiring forming process of a semiconductor device according to a conventional damascene method.

도2a 내지 2e는 본 발명의 일실시예에 따른 반도체 소자의 금속배선 형성 공정 단면도2A through 2E are cross-sectional views of a metal wiring forming process of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings

20: 반도체 기판 21: 제1 절연막20: semiconductor substrate 21: first insulating film

22: 제2 절연막 23: 금속막22: second insulating film 23: metal film

40: 감광막 패턴40: photosensitive film pattern

상기 목적을 달성하기 위한 본 발명은 반도체 기판 상의 금속배선 위치에 감광막 패턴을 형성하는 제1 단계; 상기 제1 단계가 완료된 전체 구조 상에 제1 절연막을 형성하는 제2 단계; 상기 감광막 패턴이 노출될 때까지 상기 제1 절연막을 연마하는 제3 단계; 상기 감광막 패턴을 제거하여 상기 금속배선 위치를 노출시키는 제4 단계; 및 상기 제4 단계가 완료된 전체 구조 상에 금속막을 형성하고, 금속막을 연마하여 상기 금속배선 위치에 금속막이 남도록 하는 제5 단계를 포함하는 반도체 소자의 금속배선 형성 방법을 제공한다.The present invention for achieving the above object is a first step of forming a photosensitive film pattern on the metal wiring position on the semiconductor substrate; A second step of forming a first insulating film on the entire structure in which the first step is completed; A third step of polishing the first insulating film until the photoresist pattern is exposed; A fourth step of exposing the metal wiring position by removing the photoresist pattern; And a fifth step of forming a metal film on the entire structure in which the fourth step is completed, and polishing the metal film so that the metal film remains at the metal wiring position.

본 발명은 금속배선 위치에 감광막 패턴을 형성하고, 절연막을 증착하고 절연막을 연마하여 감광막 패턴을 노출시키고, 감광막 패턴을 제거한 다음 금속막을 증착하고 연마하여 금속배선을 형성하는 것을 특징으로 한다.The present invention is characterized by forming a photoresist pattern at a metal wiring position, depositing an insulating film and polishing the insulating film to expose the photoresist pattern, removing the photoresist pattern, and then depositing and polishing a metal film to form a metal wiring.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 바람직한 실시예를 첨부된 도면 도2a 내지 도2e를 참조하여 설명한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. Will be explained.

먼저, 도2a에 도시한 바와 같이 반도체 기판(20) 상에 1000 Å 내지 10000 Å 두께의 제1 절연막(21)을 형성하고, 제1 절연막(21) 상의 금속배선 위치에 4000 Å 내지 12000 Å 높이의 감광막 패턴(40)을 형성한 후, 제2 절연막(22)을 형성한다.First, as shown in FIG. 2A, a first insulating film 21 having a thickness of 1000 GPa to 10000 GPa is formed on the semiconductor substrate 20, and a height of 4000 GPa to 12000 GPa is formed at a metal wiring position on the first insulating film 21. After the photosensitive film pattern 40 is formed, the second insulating film 22 is formed.

상기 제1 절연막(21)은 산화질화막, 실리콘질화막(Si3N4) 또는 화학기상증착법(chemical vapor deposition)법으로 형성된 산화막이고, 상기 제2 절연막(22)은 200 ℃ 이하의 온도에서 형성된 APL(advanced planarization layer), 또는 플라즈마 화학기상증착법(plasma enhanced chemical vapor deposition)으로 형성된 산화막이거나 SOG(spin on glass)막이다.The first insulating film 21 is an oxide film formed by an oxynitride film, a silicon nitride film (Si 3 N 4 ) or a chemical vapor deposition method, and the second insulating film 22 is an APL formed at a temperature of 200 ° C. or less. It is an oxide film formed by an advanced planarization layer, or plasma enhanced chemical vapor deposition, or a spin on glass (SOG) film.

다음으로, 도2b에 도시한 바와 같이 감광막 패턴(40)이 노출될 때까지 상기 제2 절연막(22)을 화학적 기계적 연마(chemical mechanical polishing)한다.Next, as shown in FIG. 2B, the second insulating film 22 is chemically mechanically polished until the photoresist pattern 40 is exposed.

다음으로, 도2c에 도시한 바와 같이 감광막 패턴(40)을 제거하여 제2 절연막(22) 사이의 금속배선 위치를 노출시킨다. 이어서, 제2 절연막(22)의 구조를 치밀하게 하기 위한 열처리 공정을 실시하기도 한다.Next, as shown in FIG. 2C, the photosensitive film pattern 40 is removed to expose the metal wiring positions between the second insulating films 22. Subsequently, a heat treatment step for densifying the structure of the second insulating film 22 may be performed.

다음으로, 도2d에 도시한 바와 같이 텅스텐, 알루미늄 또는 구리 등의 금속막(23)을 화학기상증착법 또는 물리기상증착법(physical vapor deposition)으로 증착한다.Next, as shown in FIG. 2D, a metal film 23 such as tungsten, aluminum or copper is deposited by chemical vapor deposition or physical vapor deposition.

다음으로, 도2e에 도시한 바와 같이 금속막(23)을 연마하여 제2 절연막(22) 사이의 금속배선 위치에 금속막(12)이 남도록 한다. 이후, 제2 절연막(22)의 구조를 치밀하게 하기 위한 열처리 공정을 실시하기도 한다. 또한, 상기 금속막(23)은 그 상부에 확산방지막 또는 반사방지막을 포함하기도 한다.Next, as shown in FIG. 2E, the metal film 23 is polished so that the metal film 12 remains at the metal wiring position between the second insulating films 22. Subsequently, a heat treatment step for densifying the structure of the second insulating film 22 may be performed. In addition, the metal layer 23 may include a diffusion barrier or an antireflection layer thereon.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은, 식각선택비를 고려하지 않으므로, 얇은 두께의 감광막 패턴을 사용할 수 있고, 절연막의 식각없이 금속배선 형성 위치를 정의하므로 식각 과정에서 감광막 패턴이 쓰러지는 것을 방지할 수 있으며, 감광막 패턴의 높이로 금속배선의 높이가 정의됨으로써 의도한 높이로 금속배선을 형성할 수 있다.In the present invention made as described above, since the etching selectivity is not considered, a thin photoresist pattern may be used, and a metal wiring formation position is defined without etching the insulating layer, thereby preventing the photoresist pattern from falling down during the etching process. As the height of the metal wiring is defined as the height of the photoresist pattern, the metal wiring can be formed at the intended height.

Claims (6)

반도체 소자의 금속배선 형성 방법에 있어서,In the metal wiring formation method of a semiconductor element, 반도체 기판 상의 금속배선 위치에 감광막 패턴을 형성하는 제1 단계;Forming a photoresist pattern at a metal wiring position on the semiconductor substrate; 상기 제1 단계가 완료된 전체 구조 상에 제1 절연막을 형성하는 제2 단계;A second step of forming a first insulating film on the entire structure in which the first step is completed; 상기 감광막 패턴이 노출될 때까지 상기 제1 절연막을 연마하는 제3 단계;A third step of polishing the first insulating film until the photoresist pattern is exposed; 상기 감광막 패턴을 제거하여 상기 금속배선 위치를 노출시키는 제4 단계; 및A fourth step of exposing the metal wiring position by removing the photoresist pattern; And 상기 제4 단계가 완료된 전체 구조 상에 금속막을 형성하고, 금속막을 연마하여 상기 금속배선 위치에 금속막이 남도록 하는 제5 단계A fifth step of forming a metal film on the entire structure of the fourth step and polishing the metal film to leave the metal film at the metal wiring position; 를 포함하는 반도체 소자의 금속배선 형성 방법.Metal wiring forming method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제2 단계에서,In the second step, 상기 제1 절연막을 200 ℃가 넘지 않는 온도에서 형성하는 반도체 소자의 금속배선 형성 방법.The metal wiring formation method of the semiconductor element which forms a said 1st insulating film at the temperature which does not exceed 200 degreeC. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 제1 절연막은 APL(advanced planarization layer), 플라즈마 화학기상증착법(plasma enhanced chemical vapor deposition)으로 형성된 산화막 또는 SOG(spin on glass)막 중 어느 하나로 형성하는 반도체 소자의 금속배선 형성 방법.The first insulating layer may be formed of any one of an advanced planarization layer (APL), an oxide film formed by plasma enhanced chemical vapor deposition, or a spin on glass (SOG) film. 제 3 항에 있어서,The method of claim 3, wherein 상기 제1 단계에서,In the first step, 상기 감광막 패턴을 상기 반도체 기판 상에 형성된 제2 절연막 상에 형성하는 반도체 소자의 금속배선 형성 방법.And forming the photosensitive film pattern on the second insulating film formed on the semiconductor substrate. 제 4 항에 있어서,The method of claim 4, wherein 상기 제2 절연막은 산화질화막, 실리콘질화막(Si3N4) 또는 화학기상증착법(chemical vapor deposition)법으로 형성된 산화막 중 어느 하나인 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.And the second insulating film is any one of an oxide film formed by an oxynitride film, a silicon nitride film (Si 3 N 4 ), or a chemical vapor deposition method. 제 3 항에 있어서,The method of claim 3, wherein 상기 제4 단계 또는 상기 제5 단계 후,After the fourth or fifth step, 상기 제1 절연막을 구조를 치밀하게 하기 위한 열처리 공정을 실시하는 제6 단계를 더 포함하는 반도체 소자의 금속배선 형성 방법.And a sixth step of performing a heat treatment process for densifying the structure of the first insulating film.
KR1019980024710A 1998-06-29 1998-06-29 Method for forming metal wiring of semiconductor device using large machine KR100296132B1 (en)

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