KR100226755B1 - Interconnection structure and manufacturing method of the same in semiconductor device - Google Patents
Interconnection structure and manufacturing method of the same in semiconductor device Download PDFInfo
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- KR100226755B1 KR100226755B1 KR1019960031638A KR19960031638A KR100226755B1 KR 100226755 B1 KR100226755 B1 KR 100226755B1 KR 1019960031638 A KR1019960031638 A KR 1019960031638A KR 19960031638 A KR19960031638 A KR 19960031638A KR 100226755 B1 KR100226755 B1 KR 100226755B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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Abstract
본 발명은 반도체 소자에 관한 것으로 특히, 금속층간의 접촉부를 개량하도록 한 반도체 소자의 금속배선 구조 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a metal wiring structure and a manufacturing method of a semiconductor device for improving contact between metal layers.
본 발명의 반도체 소자의 금속배선 구조는 기판상에 형성되는 절연막과, 상기 절연막상에 일정한 간격을 갖고 일방향으로 형성되는 제 1 금속배선과, 상기 제 1 금속배선의 양측면에 형성되는 측벽 스페이서와, 그리고 상기 제 1 금속배선과 전기적으로 연결되도록 상기 제 1 금속배선과 수직한 방향으로 형성되는 제 2 금속배선을 포함하여 형성됨을 특징으로 한다.The metallization structure of the semiconductor device of the present invention includes an insulating film formed on a substrate, a first metal wiring formed in one direction at regular intervals on the insulating film, sidewall spacers formed on both sides of the first metal wiring, And a second metal wire formed in a direction perpendicular to the first metal wire so as to be electrically connected to the first metal wire.
Description
본 발명은 반도체 소자에 관한 것으로 특히, 금속배선간의 접촉부를 개선하여 소자의 신뢰성을 향상시키는데 적당하도록한 반도체 소자의 금속배선 구조 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a metal wiring structure and a manufacturing method of a semiconductor device adapted to improve the reliability of the device by improving the contact portion between the metal wires.
일반적으로 알루미늄(Aluminum)과 그 합금박막은 전기 전도도가 높고, 건식식각(Dry Etch)에 의한 패턴형성이 용이하며, 실리콘 산화막과의 접착성이 우수한 동시에 가격이 저렴하므로 반도체 회로의 배선재료로서 널리 사용되어 왔다.In general, aluminum and its alloy thin films are widely used as wiring materials for semiconductor circuits because they have high electrical conductivity, easy pattern formation by dry etching, good adhesion with silicon oxide films, and low cost. Has been used.
그러나 집적회로의 집적도가 증가함에 따라 소자의 크기가 감소하고 배선이 미세화, 다층화 되므로 토폴로지(Topology)를 갖는 부분이나 콘택홀(Contact Hole) 또는 비아홀(Via Hole) 등의 접속구멍 내부에서 스텝커버레이지(Step Coverage)가 중요하게 되었다.However, as the degree of integration of integrated circuits increases, the size of devices decreases and wiring becomes finer and multi-layered. Therefore, the step cover layer inside a connection hole such as a contact hole or via hole, such as a topology, a contact hole or a via hole (Step Coverage) has become important.
즉, 기존의 금속배선막 형성방법인 스퍼터링(Sputtering)을 적용하면 단차를 갖는 부분에서 쉐도우(Shadow) 효과에 의해 부분적으로 배선막의 두께가 얇게 형성되며, 특히 종횡비(Aspect Ratio)가 1 이상인 콘택홀에서 더욱 심하게 나타난다.That is, when the sputtering method, which is a conventional metal wiring film forming method, is applied, the thickness of the wiring film is partially formed by the shadow effect in the part having the step, and in particular, the contact hole having an aspect ratio of 1 or more More severe in.
그러므로 이러한 물리적 증착방법 대신에 균일한 두께로 증착할 수 있는 화학기상증착법이 도입되어 텅스텐막을 저압화학기상증학(LPCVD : Low Pressure Chemi cal Vapotr Deposition)법으로 형성함으로써 스텝커버레이지(Step Coverage)를 개선하는 연구개발이 진행되었으나 텅스텐 배선막은 알루미늄 배선막에 비해 비저항(Resistivity)이 2배 이상되므로 배선막으로서의 적용이 어렵다.Therefore, instead of the physical vapor deposition method, a chemical vapor deposition method capable of depositing a uniform thickness is introduced to form a tungsten film by low pressure chemical vapor deposition (LPCVD) to improve step coverage. Although the research and development has been progressed, the tungsten wiring film has a resistivity of more than twice that of the aluminum wiring film, and thus it is difficult to be applied as a wiring film.
따라서 접속구멍에 매몰층(Plug)을 형성하여 이를 이용하여 금속배선을 형성하는 방법이 개발되고 있다.Therefore, a method of forming a buried layer (Plug) in the connection hole to form a metal wiring by using it has been developed.
이에 대하여 화학기상증착법으로 알루미늄을 위주로 하는 배선막을 형성하게 되면 스텝커버레이지가 개선되는 동시에 사진식각공정(Photolithorgraphy and Etching)등 기존의 스퍼터링에 의한 알루미늄 배선막 기술의 주변관련 공정과의 연속성을 유지할 수 있으므로 유리하다.On the other hand, if the aluminum-based wiring film is formed by chemical vapor deposition, the step coverage can be improved and the continuity with the surrounding process of the aluminum wiring film technology by conventional sputtering such as photolithorgraphy and etching can be maintained. So it is advantageous.
이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 금속배선 구조 및 제조방법을 설명하면 다음과 같다.Hereinafter, a metal wiring structure and a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1은 종래의 반도체 소자의 금속배선의 레이아웃도이고, 도 2는 도 1의 A-A'에 따른 구조단면도이다.FIG. 1 is a layout diagram of a metal wiring of a conventional semiconductor device, and FIG. 2 is a structural cross-sectional view taken along line AA ′ of FIG. 1.
종래의 반도체 소자의 금속배선은 도 1 및 도 2에 도시된 바와 같이, 반도체 기판(11)상에 절연막(12)이 형성되고, 상기 절연막(12)상에 일정간격을 갖고 일방향으로 제 1 금속배선(14)이 형성된다.1 and 2, an insulating film 12 is formed on a semiconductor substrate 11, and a first metal in one direction has a predetermined interval on the insulating film 12. The wiring 14 is formed.
그리고 상기 제 1 금속배선(14)을 포함한 전면에 층간 절연막(15)이 상기 제 1 금속배선(14)상에 콘택홀(17)갖고 형성되고, 상기 콘택홀(17)을 통해 상기 제 1 금속배선(14)과 전기적으로 연결되도록 상기 제 1 금속배선(14)과 수직한 방향으로 제 2 금속배선(18)이 형성된다.An interlayer insulating layer 15 is formed on the entire surface including the first metal wire 14 with the contact hole 17 on the first metal wire 14 and through the contact hole 17. The second metal wire 18 is formed in a direction perpendicular to the first metal wire 14 so as to be electrically connected to the wire 14.
도 3a - 도 3e는 종래의 반도체 소자의 금속배선 제조방법을 나타낸 공정단면도이다.3A to 3E are cross-sectional views illustrating a method for manufacturing metal wirings of a conventional semiconductor device.
종래의 반도체 소자의 금속배선 제조방법은 먼저 도 3a에 도시된 바와 같이, 반도체 기판(11)상의 전면에 절연막(12)을 형성하고, 상기 절연막(12)상의 전면에 제 1 금속배선(13)을 형성한다.In the conventional method of manufacturing metal wiring of a semiconductor device, as shown in FIG. 3A, an insulating film 12 is formed on the entire surface of the semiconductor substrate 11, and the first metal wiring 13 is formed on the entire surface of the insulating film 12. To form.
이어서, 도 3b에 도시된 바와 같이, 감광막(도면에 도시하지 않음)을 도포한 후, 사진석판술(Photolithorgraphy) 및 식각공정에 의해 상기 제 1 금속배선을 알루미늄층(13)을 선택적으로 제거하여 일정한 간격을 갖는 제 1 금속배선(14)을 형성하고 감광막은 제거한다.Subsequently, as shown in FIG. 3B, after applying a photoresist film (not shown), the first metal wiring is selectively removed by the photolithorgraphy and etching processes. The first metal wiring 14 having a predetermined interval is formed and the photosensitive film is removed.
다음에, 도 3c에 도시된 바와 같기 상기 제 1 금속배선(14)을 포함한 전면에 PECVD(Plasma Enhanced Chemical Vapor Deposition)법으로 층간 절연을 위한 층간절연막(15)을 형성한다.Next, as shown in FIG. 3C, an interlayer insulating film 15 for interlayer insulation is formed on the entire surface including the first metal wiring 14 by PECVD (Plasma Enhanced Chemical Vapor Deposition).
이어서 도 3d에 도시된 바와 같이 상기 층간 절연막(15)상에 감광막(16)을 도포한 후, 노광 및 현상공적으로 패터닝하고, 상기 패터닝된 감광막(16)을 마스크로 이용하여 상기 제 1 금속배선(14) 표면에 소정부분이 노출되도록 상기 층간 절연막(15)을 선택적으로 제거하여 곤택홀(17)을 형성한다.Subsequently, as shown in FIG. 3D, the photoresist film 16 is coated on the interlayer insulating film 15, and then patterned by exposure and development, and the first metal wiring using the patterned photoresist film 16 as a mask. (14) The contact hole 17 is formed by selectively removing the interlayer insulating film 15 so that a predetermined portion is exposed on the surface.
그리고 도 3e에 도시된 바와 같이 상기 감광막(16)을 제거하고, 상기 콘택홀(17)을 포함한 전면에 제 2 금속 배선용 알루미늄층을 증착하여 상기 콘택홀(17)을 통해 제 1 금속배선(14)과 전기적으로 연결되도록 감광막을 이용한 사진석판술 및 식각공정으로 상기 제 2 금속배선용 알루미늄층을 선택적으로 제거하여 제 2 금속배선(18)을 형성한다.As shown in FIG. 3E, the photoresist film 16 is removed, and a second metal wiring aluminum layer is deposited on the entire surface including the contact hole 17, thereby forming the first metal wire 14 through the contact hole 17. Photolithography and etching process using a photosensitive film so as to be electrically connected to the second) to selectively remove the second metal wiring aluminum layer to form a second metal wiring (18).
그러나 이와 같은 종래의 반도체 소자의 금속배선 구조 및 제조방법에 있어서 다음과 같은 문제점이 있었다.However, the metal wiring structure and manufacturing method of the conventional semiconductor device has the following problems.
즉, 수직으로 식각된 접촉부 층간 절연막의 측면을 따라 제 2 배선금속이 증착되므로써 증착된 제 2 금속배선의 나쁜 스텝커버레이지(Step Coverage)때문에 배선의 단선이나 접촉부 저항이 증가할 위험이 높다.That is, since the second wiring metal is deposited along the side surface of the vertically etched contact interlayer insulating layer, there is a high risk of disconnection or contact resistance of the wiring due to bad step coverage of the second metal wiring deposited.
또한, 수직으로 식각되므로 평면의 불규칙을 가져온다.It also etches vertically, resulting in plane irregularities.
본 발명은 이와 같은 문제점을 해결하기 위해 안출한 것으로 제 1차 배선에 측벽을 형성하여 단차 피복성을 줄이고, 스텝커버레이지를 향상시키도록 한 반도체 소자의 금속 배선 구조 및 제조방법을 제공하는데 목적이 있다.Disclosure of Invention The present invention has been made to solve such a problem, and an object of the present invention is to provide a metal wiring structure and a manufacturing method of a semiconductor device to form sidewalls in the first wiring to reduce step coverage and to improve step coverage. have.
제1도는 종래의 반도체 소자의 금속배선 레이아웃도.1 is a metal wiring layout diagram of a conventional semiconductor device.
제2도는제1도는하여금 A-A' 선에 따른 구조단면도.2 is a structural cross-sectional view taken along line A-A 'of FIG.
제3a-3e도는 종래의 반도체 소자의 금속배선 제조방법을 나타낸공정단면도.3A-3E are process cross-sectional views showing a method for manufacturing metal wirings of a conventional semiconductor device.
제4도는 본 발명의 반도체 소자의 금속배선 레이아웃도.4 is a layout diagram of the metallization of the semiconductor device of the present invention.
제5도는 제4도의 B-B'선에 따른 구조단면도.5 is a structural cross-sectional view taken along the line B-B 'of FIG.
도6a - 도3d는 본 발명의 반도체 소자의 금속배선 제조방법을 나타낸 공정단면도.6A through 3D are cross-sectional views illustrating a method for manufacturing metal wirings of a semiconductor device of the present invention.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
21 ： 반도체 기판 22 ： 절연막21: semiconductor substrate 22: insulating film
24 ： 제 1 금속배선 25 ： 측벽 스페이서24: 1st metal wiring 25: Side wall spacer
26 ： 제 2 금속배선26 ： Second metal wiring
상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 금속배선 구조는 기판상의 형성되는 절연막고, 상기 절연막사에 일정한 간격을 갖고 일방향으로 형성되는 제 1 금속배선과, 상기 제 1 금속배선의 양측면에 형성되는 측벽 스페이서와, 그리고 상기 제 1 금속배선과 전기적으로 연결되도록 상기 제 1 금속배선과 수직한 방향으로 형성되는 제 2 금속배선을 포함하여 형성되고, 상기와 같은 구조를 갖는 반도체 소자의 금속배선 제조방법은 기판상에 절연막을 형성하는 단계와, 상기 절연막상에 일정한 간격을 갖는 제 1 금속배선을 형성하는 단계와, 상기 제 1 금속배선을 포함한 전면에 층간절연막을 형성하고 전면에 에치백 공정을 실시하여 상기 제 1 금속배선의 양측면에 측벽 스페이서를 형성하는 단계와, 상기 제 1 금속배선과 전기적으로 연결되도록 제 2 금속배선을 형성하는 단계를 포함하여 형성함을 특징으로 한다.The metal wiring structure of the semiconductor device of the present invention for achieving the above object is an insulating film formed on a substrate, the first metal wiring formed in one direction at regular intervals in the insulating film yarn, and both sides of the first metal wiring A metal wiring of a semiconductor device having a structure as described above, the sidewall spacer being formed and a second metal wiring formed in a direction perpendicular to the first metal wiring so as to be electrically connected to the first metal wiring. The manufacturing method includes forming an insulating film on a substrate, forming a first metal wiring having a predetermined interval on the insulating film, forming an interlayer insulating film on the entire surface including the first metal wiring, and etching back the entire surface. Forming sidewall spacers on both side surfaces of the first metal wiring to be electrically connected to the first metal wiring; The lock is characterized in that the formation, including the step of forming a second metal wiring.
이, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 금속배선 구조 및 제조방법을 상세히 설명하면 다음과 같다.The metal wiring structure and manufacturing method of the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 4 는 본 발명의 반도체 소자의 금속배선 레이아웃도이고, 도 5 는 도 4의 B-B'선에 따른 구조단면도이다.4 is a layout diagram of the metallization of the semiconductor device of the present invention, and FIG. 5 is a cross-sectional view taken along the line BB ′ of FIG. 4.
본 발명의 반도체 소자의 금속배선은 도 4 및 도 5에 도시된 바와 같이 반도체 기판(21)상에 절연막(22)이 형성되고, 상기 절연막(22)상에 일정한 간격을 갖고 일방향으로 제 1 금속배선(24)이 형성된다.In the metal wiring of the semiconductor device of the present invention, as shown in FIGS. 4 and 5, an insulating film 22 is formed on the semiconductor substrate 21, and the first metal is disposed on the insulating film 22 in one direction at regular intervals. The wiring 24 is formed.
그리고 상기 제 1 금속배선(24)의 양측면에 스페이서 측벽(25)이 형성되고, 상기 스페이서 측벽(25)을 지나 상기 제 1 금속배선(24)과 전기적으로 연결되도록 상기 제 1 금속배선(24)과 수직한 방향으로 제 2 금속배선(26)이 형성된다.Spacer sidewalls 25 are formed on both side surfaces of the first metal line 24, and the first metal line 24 is electrically connected to the first metal line 24 through the spacer side wall 25. The second metal wire 26 is formed in a direction perpendicular to the second metal wire 26.
도 6a - 도 6e는 본 발명의 반도체 소자의 금속배선 제조방법을 나타낸 공정단면도이다.6A through 6E are cross-sectional views illustrating a method of manufacturing metal wirings in a semiconductor device of the present invention.
본 발명의 반도체 소자의 금속배선 제조방법은 먼저 도 6a에 도시된 바와 같이, 반도체 기판(21)상에 절연막(22)을 형성하고, 상기 절연막(22)상에 제 1 금속배선용 알루미늄층(23)을 형성한다.In the method of manufacturing a metal wiring of the semiconductor device of the present invention, first, as shown in FIG. 6A, an insulating film 22 is formed on a semiconductor substrate 21, and a first metal wiring aluminum layer 23 is formed on the insulating film 22. ).
이어서, 도 6b에 도시된 바와 같이, 제 1 금속배선용 알루미늄층(23)상에 감광막(도면에 도시하지 않음)을 도포한 후, 노광 및 현상공정으로 패터닝하고, 상기 패터닝된 감광막을 마스크로 이용하여 상기 제 1 금속배선용 알루미늄층(23)을 선택적으로 제거하므로써 일정간격을 갖는 제 1 금속배선(24)을 형성한다.Subsequently, as shown in FIG. 6B, a photoresist film (not shown) is applied onto the first metal wiring aluminum layer 23, and then patterned by an exposure and development process, and the patterned photoresist film is used as a mask. By selectively removing the first metal wiring aluminum layer 23, the first metal wiring 24 having a predetermined interval is formed.
다음에, 도 6c에 도시된 바와 같기 상기 제 1 금속배선(24)을 포함한 반도체 기판(21)의 전면에 층간절연을 위한 층간 절연막을 증착한 다음, 에치백(Etch Back) 공정을 실시하여 상기 제 1 금속배선(24)의 양측면에 측벽 스페이서(25)를 형성한다.Next, as shown in FIG. 6C, an interlayer insulating film for interlayer insulation is deposited on the entire surface of the semiconductor substrate 21 including the first metal wiring 24, and then subjected to an etch back process. Sidewall spacers 25 are formed on both side surfaces of the first metal wire 24.
그리고 도 6d에 도시된 바와 같이, 상기 제 1 금속배선(24) 및 측벽 스페이서(25)를 포함한 반도체 기판(21)의 전면에 제 2금속배선용 알루미늄층을 증착하고, 상기 제 1금속배선(24)과 전기적으로 연결되도록 선택적으로 제거하므로써 제 2 금속배선(26)을 형성한다.6D, an aluminum layer for second metal wiring is deposited on the entire surface of the semiconductor substrate 21 including the first metal wiring 24 and the sidewall spacer 25, and the first metal wiring 24 is deposited. The second metal wire 26 is formed by selectively removing the wires to be electrically connected to each other.
이상에서 설명한 바와 같이 본 발명의 반도체 소자의 금속배선 구조 및 제조방법은 다음과 같은 효과가 있다.As described above, the metallization structure and manufacturing method of the semiconductor device of the present invention have the following effects.
첫째, 접촉부의 절연막 제거시 제 2 금속배선이 형성될 제 1 금속배선상의 절연막을 함께 제거함으로써 반도체 소자의 평탄화를 가져온다.First, when the insulating film of the contact portion is removed, the insulating film on the first metal wiring, on which the second metal wiring is to be formed, is removed together, resulting in flattening of the semiconductor device.
둘째, 제 1 금속배선의 양측면에 측벽 스페이서를 형성하므로써 스텝커버레이지(Step Coverage)를 향상시킨다.Second, the step coverage is improved by forming sidewall spacers on both sides of the first metal wiring.
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