KR0147466B1 - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing methodInfo
- Publication number
- KR0147466B1 KR0147466B1 KR1019950012101A KR19950012101A KR0147466B1 KR 0147466 B1 KR0147466 B1 KR 0147466B1 KR 1019950012101 A KR1019950012101 A KR 1019950012101A KR 19950012101 A KR19950012101 A KR 19950012101A KR 0147466 B1 KR0147466 B1 KR 0147466B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating layer
- forming
- side wall
- gate
- wall spacer
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
Abstract
본 발명은 반도체장치의 제조방법에 관한 것으로, 살리사이드방법을 이용하여 비트라인 콘택을 형성하는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a bit line contact is formed using a salicide method.
본 발명은 제1도전형 반도체기판상에 게이트산화막을 형성하는 공정과, 상기 게이트산화막 상부 소정영역에 게이트를 형성하는 공정, 제2도전형 불순물을 이온주입하는 공정, 상기 게이트 측면에 제1측벽스페이서를 형성하는 공정, 전이금속을 이온주입하고 열처리하는 공정, 사이 제1측벽스페이서 측면에 제2측벽스페이서를 형성하는 공정, 기판 전면에 제1절연층과 제2절연층을 차례로 형성하는 공정, 상기 제2절연층 및 제1절연층을 선택적으로 식각하여 기판 소정부분을 노출시키는 비트라인 콘택을 형성하는 공정으로 이루어지는 반도체장치의 제조방법을 제공한다.The present invention provides a process for forming a gate oxide film on a first conductive semiconductor substrate, forming a gate in a predetermined region over the gate oxide film, implanting a second conductive impurity, and a first side wall on the side of the gate. Forming a spacer, ion implanting and heat treating a transition metal, forming a second side wall spacer on the side of the first side wall spacer, forming a first insulating layer and a second insulating layer on the entire surface of the substrate in turn; A method of manufacturing a semiconductor device, comprising forming a bit line contact to selectively expose a predetermined portion of a substrate by selectively etching the second insulating layer and the first insulating layer.
Description
제1도는 종래의 DRAM셀 제조방법을 도시한 공정순서도1 is a process flowchart showing a conventional DRAM cell manufacturing method
제2도는 본 발명에 의한 DRAM셀 제조방법을 도시한 공정순서도2 is a process flowchart showing a DRAM cell manufacturing method according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:게이트산화막 2:게이트1: gate oxide film 2: gate
4:제1측벽스페이서 5:n형불순물영역4: first side wall spacer 5: n-type impurity region
6:제1절연층 7:제2절연층6: first insulating layer 7: second insulating layer
8:포토레지스트 9:실리사이드8: Photoresist 9: Silicide
10:폴리사이드 11:제2측벽스페이서10: polyside 11: second side wall spacer
본 발명은 반도체 장치의 제조방법에 관한 것으로, 특히 DRAM(Dynamic Random Access Memory)의 비트라인 콘택(Bit line contact)형성방법에 관한 것이다. 종래의 64M DRAM 비트라인 형성방법을 제1도를 참조하여 설명하면 다음과 같다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a bit line contact of a DRAM (Dynamic Random Access Memory). A conventional method of forming a 64M DRAM bit line will now be described with reference to FIG.
먼저, 제1도 (a)에 도시된 바와 같이 필드산화막(102)에 의해 소자분리영역과 활성영역으로 구분된 p형 반도체기판(101)상에 게이트산화막(1)을 형성하고, 그위에 게이트 형성을 위한 도전층으로 폴리실리콘을 증착한 후, 이위에 산화막을 형성한 다음 산화막 및 폴리실리콘층을 소정의 게이트패턴으로 패터닝하여 게이트(2)와 캡산화막(3)을 형성한다. 이어서 n형 불순물을 이온주입하여 소오스 및 드레인영역이 되는 n형 불순물영역(5)을 형성한 후, 기판 전면에 절연막을 증착하고 이를 에치백하여 게이트 측면에 측벽스페이서(4)를 형성한 다음, 기판 전면에 제1절연층(6)을 형성한다.First, as shown in FIG. 1A, a gate oxide film 1 is formed on a p-type semiconductor substrate 101 divided into a device isolation region and an active region by a field oxide film 102, and a gate thereon. After depositing polysilicon as a conductive layer for formation, an oxide film is formed thereon, and then the oxide film and the polysilicon layer are patterned into a predetermined gate pattern to form the gate 2 and the cap oxide film 3. Subsequently, an n-type impurity region 5 is formed by ion implantation of the n-type impurity, and then an insulating film is deposited on the entire surface of the substrate and etched back to form a sidewall spacer 4 on the side of the gate. The first insulating layer 6 is formed on the entire surface of the substrate.
이어서 제1도 (b)에 도시된 바와 같이 상기 제1절연층(6)을 에치백에 의해 평탄화한 후, 그위에 제2절연층(7)을 형성한 다음 포토레지스트(8)를 도포한다. 이어서 사진공정을 통해 포토레지스트에 소정의 비트라인 콘택패턴을 전사시켜 포토레지스트패턴을 형성한 후, 이 포토레지스트패턴을 마스크로 하여 제2절연층(7) 및 제1절연층(6)을 식각하여 상기 n형 불순물영역(5)을 노출시키는 비트라인 콘택을 형성한다.Subsequently, as shown in FIG. 1 (b), the first insulating layer 6 is flattened by etch back, a second insulating layer 7 is formed thereon, and then the photoresist 8 is applied. . Subsequently, a predetermined bit line contact pattern is transferred to the photoresist through a photo process to form a photoresist pattern, and the second insulating layer 7 and the first insulating layer 6 are etched using the photoresist pattern as a mask. As a result, a bit line contact exposing the n-type impurity region 5 is formed.
이와 같은 종래의 비트라인콘택 형성방법에 있어서는 포토레지스트패턴을 형성한 후 이를 이용하여 그 하부층을 저스트 에치(just etch)하기 때문에 미스얼라인(mis-align)의 위험성을 안고 있다.In such a conventional bit line contact forming method, since the photoresist pattern is formed and then the lower layer is just etched using the photoresist pattern, there is a risk of misalignment.
본 발명은 이와 같은 문제를 해결하기 위한 것으로, 살리사이드(salicide; self-aligned silicide)방법을 이용하여 비트라인 콘택을 형성하는 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of forming a bit line contact by using a salicide (self-aligned silicide) method.
상기 목적을 달성하기 위한 본 발명의 반도체장치의 제조방법은 제1도전형 반도체기판상에 게이트산화막을 형성하는 공정과, 상기 게이트산화막 상부 소정영역에 게이트를 형성하는 공정, 제2도전형 불순물을 이온주입하는 공정, 상기 게이트 측면에 제1측벽스페이서를 형성하는 공정, 전이금속을 도포하거나 이온 주입하고 열처리하는 공정, 상기 제1측벽스페이서 측면에 제2측벽스페이서를 형성하는 공정, 기판 전면에 제1절연층과 제2절연층을 차례로 형성하는 공정, 상기 제2절연층 및 제1절연층을 선택적으로 식각하여 기판 소정부분을 노출시키는 비트라인 콘택을 형성하는 공정, 및 상기 제2측벽스페이서를 제거하는 공정으로 이루어진다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a gate oxide film on a first conductive semiconductor substrate, forming a gate in a predetermined region on the gate oxide film, and a second conductive impurity Ion implantation, forming a first sidewall spacer on the side of the gate, applying or ion implanting and heat treating a transition metal, forming a second sidewall spacer on the side of the first sidewall spacer, Forming a first insulating layer and a second insulating layer in sequence, selectively etching the second insulating layer and the first insulating layer to form a bit line contact to expose a predetermined portion of the substrate, and the second side wall spacer Removal process.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도에 본 발명에 의한 DRAM의 비트라인 콘택 형성방법을 도시하였다.2 illustrates a method for forming a bit line contact of a DRAM according to the present invention.
먼저, 제2도 (a)에 도시된 바와 같이 필드산화막(102)에 의해 소자분리영역과 활성영역으로 구분된 p형 반도체기판(101)상에 게이트산화막(1)을 형성하고, 그위에 게이트 형성을 위한 도전층으로 폴리실리콘을 증착한 후, 소정의 게이트패턴으로 상기 폴리실리콘층 및 게이트산화막을 패터닝하여 게이트(2)를 형성한다.First, as shown in FIG. 2A, a gate oxide film 1 is formed on a p-type semiconductor substrate 101 divided into a device isolation region and an active region by a field oxide film 102, and a gate thereon. After depositing polysilicon as a conductive layer for formation, the polysilicon layer and the gate oxide film are patterned with a predetermined gate pattern to form the gate 2.
이어서 제2도 (b)에 도시된 바와 같이 n형 불순물을 이온주입하여 소오스 및 드레인영역이 되는 n형 불순물영역(5)을 형성한 후, 기판 전면에 절연막으로서, 예컨대 산화막을 증착하고 이를 에치백하여 게이트 측면에 제1측벽스페이서(4)를 형성한다.Subsequently, as shown in FIG. 2 (b), n-type impurities are ion-implanted to form n-type impurity regions 5 serving as source and drain regions, and then, as an insulating film, for example, an oxide film is deposited on the entire surface of the substrate. The back side is formed to form a first side wall spacer 4 on the side of the gate.
다음에 제2도 (c)에 도시된 바와 같이 전이금속으로서, 예컨대 Co, Ni, Cr, Ti, W등을 도포하거나 이온주입하고 열처리하여 n형 불순물영역(5)상에는 실리사이드(9)가, 그리고 게이트(2)상에는 폴리사이드(10)가 형성되도록 한다.Next, as shown in FIG. 2 (c), as the transition metal, for example, Co, Ni, Cr, Ti, W, or the like is applied or ion implanted and heat treated, so that the silicide 9 is formed on the n-type impurity region 5, In addition, a polyside 10 is formed on the gate 2.
이어서 제2도 (d)에 도시된 바와 같이 기판 전면에 상기 제1측벽스페이서(4)에 대해 식각 선택성(selectivity)이 큰 절연물질로서, 예컨대 질화막을 증착한 후, 에치백하여 제1측벽스페이서 측면에 제2측벽스페이서(11)를 형성한다. 이때, 제2측벽스페이서(11) 형성을 위한 에치백시 게이트상부의 폴리사이드(10)가 식각저지층으로 작용한다.Subsequently, as shown in FIG. 2 (d), an insulating material having a high etch selectivity with respect to the first side wall spacer 4 on the entire surface of the substrate, for example, a nitride film is deposited and then etched back to form the first side wall spacer. The second side wall spacers 11 are formed on the side surfaces. At this time, the polyside 10 on the gate during etching back to form the second side wall spacer 11 serves as an etch stop layer.
다음에 제2도 (e)에 도시된 바와 같이 기판 전면에 제1절연층(6)으로서, 예컨대 산화막을 형성하고 이 산화막을 에치백에 의해 평탄화한 후, 그위에 제2절연층(7)으로서, 예컨대 산화막을 형성한 다음 포토레지스트(8)를 도포한다. 이때, 상기 제1절연층 및 제2절연층은 상기 제2측벽스페이서(11)에 대해 식각선택성이 큰 물질로 형성한다. 이어서 사진공정을 통해 포토레지스트(8)에 소정의 비트라인 콘택패턴을 전사시켜 포토레지스트패턴을 형성한 후, 이 포토레지스트패턴을 마스크로 하여 제2절연층(7) 및 제1절연층(6)을 식각하여 상기 n형 불순물영역(5)을 노출시키는 비트라인 콘택을 형성한다. 이때, 상기 사진식각공정시 미스얼라인이 일어나더라도 제2측벽스페이서(11)가 제1절연층(6) 및 제2절연층(7)과 식각선택성의 차이가 크기 때문에 게이트(2)와 n형 불순물영역(5)이 단락될 위험성은 없다.Next, as shown in FIG. 2E, as the first insulating layer 6, for example, an oxide film is formed on the entire surface of the substrate, the oxide film is planarized by etch back, and then the second insulating layer 7 is placed thereon. For example, an oxide film is formed and then the photoresist 8 is applied. In this case, the first insulating layer and the second insulating layer are formed of a material having a high etching selectivity with respect to the second side wall spacer 11. Subsequently, a predetermined bit line contact pattern is transferred to the photoresist 8 through a photolithography process to form a photoresist pattern, and then the second insulating layer 7 and the first insulating layer 6 are formed using the photoresist pattern as a mask. ) Is formed to form a bit line contact exposing the n-type impurity region 5. In this case, even if a misalignment occurs in the photolithography process, the gate side 2 and the n because the second side wall spacer 11 has a large difference in etching selectivity from the first insulating layer 6 and the second insulating layer 7. There is no danger that the type impurity region 5 is shorted.
다음에 제2도 (f)에 도시된 바와 같이 상기 포토레지스트패턴 및 제2측벽스페이서를 제거함으로써 비트라인 콘택을 형성한다.Next, as shown in FIG. 2 (f), the bit line contact is formed by removing the photoresist pattern and the second side wall spacer.
이상과 같이 본 발명은 살리사이드방법에 의해 비트라인콘택이 형성되는 n형불순물영역 상부에 실리사이드를 형성함으로써 비트라인의 콘택저항이 감소되는 효과를 얻을 수 있으며, 셀프얼라인 비트라인 콘택을 형성하므로 사진식각공정시 미스얼라인의 마진을 충분히 확보할 수 있고, 콘택의 크기에 대한 마진 또한 확보할 수 있다.As described above, the present invention can obtain the effect of reducing the contact resistance of the bit line by forming a silicide on the n-type impurity region where the bit line contact is formed by the salicide method, and forming a self-aligned bit line contact. The margin of misalignment can be secured sufficiently during the photolithography process, and the margin for the size of the contact can be secured.
Claims (3)
Priority Applications (1)
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| KR1019950012101A KR0147466B1 (en) | 1995-05-16 | 1995-05-16 | Semiconductor device manufacturing method |
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| KR1019950012101A KR0147466B1 (en) | 1995-05-16 | 1995-05-16 | Semiconductor device manufacturing method |
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| KR960043203A KR960043203A (en) | 1996-12-23 |
| KR0147466B1 true KR0147466B1 (en) | 1998-08-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100672784B1 (en) * | 2005-06-29 | 2007-01-22 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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1995
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100672784B1 (en) * | 2005-06-29 | 2007-01-22 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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| KR960043203A (en) | 1996-12-23 |
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