KR940001255B1 - Method of making capacitor of semiconductor memory device - Google Patents
Method of making capacitor of semiconductor memory device Download PDFInfo
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- KR940001255B1 KR940001255B1 KR1019910016078A KR910016078A KR940001255B1 KR 940001255 B1 KR940001255 B1 KR 940001255B1 KR 1019910016078 A KR1019910016078 A KR 1019910016078A KR 910016078 A KR910016078 A KR 910016078A KR 940001255 B1 KR940001255 B1 KR 940001255B1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000003860 storage Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 39
- 229920002120 photoresistant polymer Polymers 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 17
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 8
- 230000001681 protective effect Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000009740 moulding (composite fabrication) Methods 0.000 claims 1
- 238000001259 photo etching Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000002035 prolonged effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
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Abstract
Description
제1도는 종래 반도체 메모리 소자의 캐패시터 제조공정도.1 is a manufacturing process diagram of a capacitor of a conventional semiconductor memory device.
제2도는 본 발명에 따른 반도체 메모리 소자의 캐패시터 제조공정도.2 is a capacitor manufacturing process diagram of a semiconductor memory device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : 필드산화막1: semiconductor substrate 2: field oxide film
3 : 게이트산화막 4 : 게이트전극용 다결정실리콘3: gate oxide film 4: polycrystalline silicon for gate electrode
5 : 게이트 보호산화막 6 : 제1다결정실리콘5: gate protective oxide film 6: first polycrystalline silicon
7 : 제1산화막 8,13,15,16 : 감광막7: first oxide film 8,13,15,16 photosensitive film
9,9' : 제1 및 제2불순물영역 10 : 질화막9,9 ': first and second impurity regions 10: nitride film
10' : 질화막측벽 11 : 제2산화막10 ': nitride film side wall 11: second oxide film
11' : 제2산화막측벽 12 : 제3산화막11 ': second oxide film side wall 12: third oxide film
14 : 제2다결정실리콘 17 : 유전막14 second polycrystalline silicon 17 dielectric film
18 : 제3다결정실리콘18: third polycrystalline silicon
본 발명은 반도체 메모리 소자의 캐패시터 제조방법에 관한 것으로, 특히 게이트 형성시 캐패시터 전극의 일부를 미리 형성시켜 캐패시터 용량을 증대시켜 제한된 면적 내에서 고집적화를 이룰 수 있도록 하는 반도체 메모리 소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor memory device, and more particularly, to a method of manufacturing a capacitor of a semiconductor memory device, in which a part of the capacitor electrode is formed in advance in forming a gate to increase the capacity of the capacitor to achieve high integration within a limited area. will be.
일반적으로 사용되는 종래 반도체 메모리 소자의 캐패시터 제조방법은 제1도에 도시된 바와 같이 반도체 기판(21)상에 필드 산화막(22)을 형성한 다음 전면에 게이트 산화막(23), 게이트 전극용 다결정실리콘(24) 및 게이트 보호산화막(25)을 소정 두께를 갖도록 차례로 증착한 후 감광막을 사용한 에치 공정을 통해 게이트를 형성한다.In a conventional method of manufacturing a capacitor of a semiconductor memory device, a field oxide film 22 is formed on a semiconductor substrate 21, as shown in FIG. 1, and then a gate oxide film 23 and a polysilicon for a gate electrode are formed on the front surface. (24) and the gate protective oxide film 25 are sequentially deposited to have a predetermined thickness, and then a gate is formed through an etch process using a photosensitive film.
그 다음 LDD 이온 주입 후 전면에 산화막을 증착 및 에치백하여 게이트의 측벽에 사이드월(26)을 형성하고, 전면에 이온을 주입하여 소스(27)/드레인(27')을 형성한 다음 전면에 산화막(26)을 증착시킨 후 감광막의 도포 및 사진식각 공정을 실시하여 베리드 콘택 영역을 정의한 후 상기 감광막을 마스크로서 에치를 실시하여 베리드 콘택 영역에 있는 절연막(28)을 제거한 다음 전면에 캐패시터의 스토리지 노드로 사용될 폴리실리콘(29)을 증착시킨 후 감광막(30)을 도포 및 사진식각 공정으로 스토리지 영역을 정의한다(제1도의 (a)도).After the LDD ion implantation, an oxide film is deposited and etched back on the front surface to form sidewalls 26 on the sidewalls of the gate, and ions are implanted on the front surface to form a source 27 / drain 27 'and then on the front surface. After depositing the oxide layer 26, a photoresist coating and photolithography process is performed to define a buried contact region, and then the photoresist is etched using a mask to remove the insulating layer 28 in the buried contact region, and then a capacitor on the front surface. After the deposition of the polysilicon 29 to be used as a storage node of the photosensitive film 30 is applied to the photolithography process to define the storage region (Fig. 1 (a)).
상기 공정 후 (b)도와 같이 상기 감광막(30)을 마스크로서 에시를 실시하여 감광막(30)이 도포된 이외의 부분에 있는 폴리실리콘(29)을 제거하고, 이어 감광막(30)을 제거한 다음 전면에 유전체(31), 및 플레이트전극(32)을 차례로 증착 및 에치함으로서 반도체 메모리 소자의 캐패시터 제조를 완성하게 된다.After the step (b), the photosensitive film 30 is subjected to ashing as a mask to remove polysilicon 29 in a portion other than the photosensitive film 30 is applied, and then the photosensitive film 30 is removed, and then the entire surface of the photosensitive film 30 is removed. The capacitor 31 and the plate electrode 32 are sequentially deposited and etched on the substrate, thereby completing the fabrication of the capacitor of the semiconductor memory device.
이와 같은 종래 반도체 메모리 소자의 캐패시터 제조방법은 게이트 폴리실리콘 위에 존재하는 게이트 보호산화막의 높이를 증가시켜 단차를 크게함으로서 캐패시터 용량을 증가시키게 되는데, 이 경우 캐패시터 용량을 증가하기에는 한계가 있고, 이 후의 공정에서 평탄화가 어렵게되는 문제점이 야기되는 것이다.Such a capacitor manufacturing method of a conventional semiconductor memory device increases the capacitor capacity by increasing the height of the gate protective oxide film present on the gate polysilicon, thereby increasing the capacitor capacity. In this case, there is a limit to increasing the capacitor capacity. The problem is that the flattening becomes difficult.
본 발명은 상기와 같은 문제점을 해결하기 위해 트랜지스터 게이트 형성시 스토리지 노드의 일부인 제1다결정실리콘을 게이트 보호산화막 위에 미리형성하고, 매몰 콘택에 증착된 제2다결정실리콘과 서로 연결시킴에 따라 게이트 라인 크기만큼 스토리지 노드의 길이를 증가시켜 캐패시터의 용량을 증대할 수 있도록 하는 반도체 메모리 소자의 캐패시터 제조방법을 제공하는데 본 발명의 목적이 있는 것이다.The present invention solves the above problems by forming a first polysilicon, which is a part of the storage node, on the gate protection oxide and forming a gate line size by interconnecting the second polysilicon deposited in the buried contact. It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor memory device that can increase the capacity of the capacitor by increasing the length of the storage node by as much as possible.
본 발명은 반도체 메모리 소자의 캐패시터 제조 방법에 있어서, 반도체 기판 위에 필드산화막을 형성하고, 전면에 게이트 산화막, 게이트 전극용 다결정실리콘, 게이트 보호산화막, 제1다결정실리콘, 제1산화막을 순차적으로 형성하고, 감광막의 도포 및 사진식각 공정으로 게이트 전극영역을 정의하는 단계와, 상기 감광막을 마스크로서 에치하여 게이트 전극을 형성하고, 이온주입으로 제1, 제2불순물영역을 형성한 후 질화막을 소정 두께로 형성하는 단계와, 상기 질화막을 이방성 식각하여 질화막측벽을 형성하고, 제1산화막을 식각하여 제거하는 단계와, 전면에 제2산화막을 증착 및 이방성식각하여 질화막측벽의 측면에 제2산화막측벽을 형성 및 제3산화막을 전면에 형성하고, 감광막의 도포 및 사진식각 공정으로 매몰 콘택영역을 정의하는 단계와, 상기 감광막을 마스크로서 식각하여 매몰콘택을 형성 및 전면에 제2다결정실리콘을 증착하고, 감광막의 도포 및 사진식각 공정으로 스토리지 노드전극 영역을 정의하는 단계와 , 상기 감광막을 마스크로서 제2다결정실리콘을 선택식각하여 스토리지 노드전극 영역에 제2다결정 실리콘을 잔류시키고, 감광막을 도포시키는 단계와, 상기 감광막을 제1다결정실리콘이 위치한 높이까지 식각하고, 상기 감광막을 마스크로서 에치하여 상기 감광막위에 노출된 제2산화막측벽과 제3산화막을 제거하는 단계와, 상기 제1 및 제2다결정실리콘의 노출된 표면에 유전체막을 형성하고, 상기 유전체막 위에 제3다결정실리콘을 증착하여 플레이트 전극을 형성하는 단계로 이루어진 것이다.In the method of manufacturing a capacitor of a semiconductor memory device, a field oxide film is formed on a semiconductor substrate, and a gate oxide film, a polycrystalline silicon for a gate electrode, a gate protective oxide film, a first polycrystalline silicon, and a first oxide film are sequentially formed on a front surface thereof. Defining a gate electrode region by applying a photoresist film and etching the photoresist; etching the photoresist film as a mask to form a gate electrode; forming first and second impurity regions by ion implantation; Forming the nitride film sidewall by anisotropically etching the nitride film, and removing the first oxide film by etching, and depositing and anisotropically etching the second oxide film on the entire surface to form a second oxide film sidewall on the side of the nitride film sidewall. And forming a third oxide film on the entire surface and defining a buried contact region by applying and photolithography a photoresist film; Etching the photoresist as a mask to form a buried contact and depositing a second polysilicon on the entire surface, and defining a storage node electrode region by applying and photolithography the photoresist; and using the photoresist as a mask, the second polysilicon Selectively etching to leave the second polycrystalline silicon in the storage node electrode region, applying a photoresist, etching the photoresist to a height where the first polysilicon is located, and etching the photoresist as a mask to expose the photoresist. Removing the second oxide side wall and the third oxide film, and forming a dielectric film on exposed surfaces of the first and second polycrystalline silicon, and depositing a third polycrystalline silicon on the dielectric film to form a plate electrode. will be.
이하 첨부된 도면에 의해 상세히 설명하면 다음과 같다.Hereinafter, described in detail by the accompanying drawings as follows.
제2도는 본 발명에 따른 반도체 메모리 소자의 캐패시터 제조공정도로서, 먼저 (a)도에서와 같이 반도체 기판(1)위에 필드산화막(2)을 형성하고, 전면에 게이트 산화막(3)과 게이트 전극용 다결정실리콘(4), 게이트 보호산화막(5), 제1다결정실리콘(6 ), 제1산화막(7)을 각각 소정두께를 갖도록 순차적으로 형성하고, 전면에 감광막(8)을 도포한 후 상기 감광막(8)을 사진식각하여 게이트 전극영역을 정의한다.2 is a manufacturing process diagram of a capacitor of a semiconductor memory device according to the present invention. First, as shown in (a), a field oxide film 2 is formed on a semiconductor substrate 1, and a gate oxide film 3 and a polycrystal for a gate electrode are formed on the entire surface thereof. The silicon 4, the gate protective oxide film 5, the first polycrystalline silicon 6, and the first oxide film 7 are sequentially formed to have a predetermined thickness, and the photoresist film 8 is coated on the entire surface, and then the photoresist film ( 8) is used to define the gate electrode region.
상기 공정 후 (b)도에서와 같이 상기 감광막(8)을 마스크로서 에치하여 게이트 전극을 제외한 영역의 제1산화막(7), 제1다결정실리콘(6), 게이트 보호산화막(5), 게이트 전극용 다결정실리콘(4), 게이트 산화막(3)을 순차적으로 식각하여 제거하고, 반도체기판(1)과 역도전형의 불순물을 주입하여 제1,제2불순물영역(9)(9')을 형성한 다음 반도체기판(1) 전면에 질화막(10)을 약 200~300Å 정도의 두께로 형성한다.After the process, as shown in (b), the first photoresist 7, the first polysilicon 6, the gate protective oxide 5, and the gate electrode of the region except the gate electrode are etched by etching the photoresist 8 as a mask. The polysilicon 4 and the gate oxide film 3 are sequentially etched and removed, and the first and second impurity regions 9 and 9 'are formed by implanting impurities of the semiconductor substrate 1 and the reverse conductivity type. Next, the nitride film 10 is formed on the entire surface of the semiconductor substrate 1 to a thickness of about 200 to 300 Å.
상기 공정이 완료되면 (c)도와 같이 상기 질화막(10)을 이방성 식각하여 게이트 산화막(3), 게이트 전극용 다결정실리콘(4), 게이트 보호산화막(5), 제1다결정실리콘(6), 제1산화막(7)의 측면에 질화막 측벽(10')을 형성한 후 제1산화막(7)을 식각하여 제거한다.When the process is completed, as shown in (c), the nitride film 10 is anisotropically etched to form a gate oxide film 3, a polycrystalline silicon 4 for a gate electrode, a gate protective oxide film 5, a first polysilicon 6, and After forming the nitride film sidewall 10 ′ on the side of the first oxide film 7, the first oxide film 7 is etched and removed.
그 다음 (d)도와 같이 전면에 제2산화막(11)을 소정 두께로 증착하고, (e)도와 같이 상기 제2산화막(11)을 이방성식각하여 질화막측벽(10')의 측면에 제2산화막측벽(11')을 형성한 후 다시 제3산화막(12)을 전면에 형성하고, 감광막(13)의 도포 및 사진식각 공정으로 게이트전극 상측과 게이트전극 하측사이에 매몰콘택(buried conta ct) 영역을 정의한다.Then, as shown in (d), the second oxide film 11 is deposited to a predetermined thickness on the entire surface, and as shown in (e), the second oxide film 11 is anisotropically etched to form a second oxide film on the side surface of the nitride film side wall 10 '. After the sidewalls 11 'are formed, a third oxide film 12 is formed on the entire surface, and a buried contact region is formed between the upper side of the gate electrode and the lower side of the gate electrode through the application and photolithography process of the photosensitive layer 13. Define.
이 후 (f)도와 같이 상기 감광막(13)을 마스크로서 제3산화막(12)을 선택식각하여 매몰 콘택을 형성한다음 전면에 스토리지 노드로 사용될 제2다결정실리콘(14)을 증착한 후 감광막(15)의 도포 및 사진식각 공정으로 매몰 콘택위에 스토리지 노드전극 영역을 정의한다.Thereafter, as shown in (f), the third oxide film 12 is selectively etched using the photoresist film 13 as a mask to form a buried contact, and then the second polysilicon 14 to be used as a storage node is deposited on the front surface, and then the photoresist film ( The storage node electrode region is defined on the buried contact in the application and photolithography process of 15).
상기 공정이 완료되면 (g)도와 같이 상기 감광막(13)을 마스크로서 제2다결정실리콘(14)을 선택식각하여 스토리지 노드전극 영역에 제2다결정실리콘을 잔류시키고, 다시 전면에 감광막(12)을 도포시킨다.When the process is completed, as shown in (g), the second polysilicon 14 is selectively etched using the photosensitive film 13 as a mask to leave the second polycrystalline silicon in the storage node electrode region, and then the photosensitive film 12 is placed on the entire surface. Apply.
그 다음 (h)도와 같이 감광막(15)을 제1다결정실리콘(5)이 위치한 높이까지 식각한 후 (i)도와 같이 상기 감광막(16)을 마스크로서 에치하여 감광막(16)위에 노출된 제2산화막측벽(11')과 제3산화막(12)을 제거한다.Next, as shown in (h), the photoresist film 15 is etched to the height at which the first polycrystalline silicon 5 is located, and then, as shown in (i), the photoresist film 16 is etched as a mask to expose the second photoresist on the photoresist film 16. The oxide film side wall 11 'and the third oxide film 12 are removed.
이 후 (j)도와 같이 제1 및 제2다결정실리콘(6)(14)의 노출된 표면에 유전막(17)을 형성하고, 상기 유전막(17)위에 제3다결정실리콘(18)을 증착하여 플레이트 전극을 형성함으로서 반도체 메모리 소자의 캐패서터 제조를 완료하게 된다.Thereafter, as shown in (j), a dielectric film 17 is formed on the exposed surfaces of the first and second polysilicon silicon 6 and 14, and a third polysilicon 18 is deposited on the dielectric film 17 to form a plate. By forming the electrode, the capacitor manufacturing of the semiconductor memory device is completed.
이상에서 상술한 바와 같이 본 발명은 트랜지스터 게이트 형성시 스토리지 노드의 일부인 제1다결정실리콘을 게이트 보호산화막 위에 미리 형성하고, 매몰 콘택에 증착된 제2다결정실리콘과 서로 연결시킴에 따라 게이트 라인 크기 만큼 스토리지 노드의 길이가 증가하게 되어 캐패시터의 용량을 증대함으로서 제한된 면적내에서 반도체 메모리 소자의 고집적화를 이룰 수 있는 것이다.As described above, according to the present invention, when the transistor gate is formed, the first polysilicon, which is a part of the storage node, is previously formed on the gate protection oxide layer, and is connected to the second polysilicon deposited on the buried contact, thereby storing as much as the gate line size. By increasing the length of the node to increase the capacity of the capacitor, it is possible to achieve high integration of the semiconductor memory device within a limited area.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910016078A KR940001255B1 (en) | 1991-09-16 | 1991-09-16 | Method of making capacitor of semiconductor memory device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910016078A KR940001255B1 (en) | 1991-09-16 | 1991-09-16 | Method of making capacitor of semiconductor memory device |
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| Publication Number | Publication Date |
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| KR930006915A KR930006915A (en) | 1993-04-22 |
| KR940001255B1 true KR940001255B1 (en) | 1994-02-18 |
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| KR1019910016078A KR940001255B1 (en) | 1991-09-16 | 1991-09-16 | Method of making capacitor of semiconductor memory device |
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| KR (1) | KR940001255B1 (en) |
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