KR0151190B1 - Transistor - Google Patents

Transistor

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Publication number
KR0151190B1
KR0151190B1 KR1019940024830A KR19940024830A KR0151190B1 KR 0151190 B1 KR0151190 B1 KR 0151190B1 KR 1019940024830 A KR1019940024830 A KR 1019940024830A KR 19940024830 A KR19940024830 A KR 19940024830A KR 0151190 B1 KR0151190 B1 KR 0151190B1
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KR
South Korea
Prior art keywords
gate electrode
forming
trench
gate
insulating film
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KR1019940024830A
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Korean (ko)
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KR960012573A (en
Inventor
박병주
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문정환
엘지반도체주식회사
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Priority to KR1019940024830A priority Critical patent/KR0151190B1/en
Publication of KR960012573A publication Critical patent/KR960012573A/en
Application granted granted Critical
Publication of KR0151190B1 publication Critical patent/KR0151190B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 트랜지스터 및 그 제조방법에 관한 것으로, 게이트 브릿지(bridge)를 예방하고 단차를 감소시키기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor and a method of manufacturing the same, in order to prevent a gate bridge and reduce a step.

본 발명은 반도체기판과, 상기 반도체기판 소정영역에 형성된 소정의 깊이를 가진 트렌치, 상기 트렌치내에 절연막을 개재하여 매립되어 형성된 게이트전극, 상기 게이트전극 및 기판상부에 형성된 게이트절연막, 상기 게이트절연막상부의 게이트전극 양단부위에 각각 형성된 소오스 및 드레인영역으로 이루어진 트랜지스터를 제공함으로써 단차를 없애며 메모리소자 제조공정시 페일의 주원인인 워드라인 브릿지를 근본적으로 방지할 수 있도록 한다.The present invention provides a semiconductor substrate, a trench having a predetermined depth formed in a predetermined region of the semiconductor substrate, a gate electrode formed by embedding an insulating film in the trench, a gate insulating film formed on the gate electrode and the substrate, and an upper portion of the gate insulating film. By providing a transistor comprising a source and a drain region formed at both ends of the gate electrode, the step is eliminated and the word line bridge, which is the main cause of the failure, can be fundamentally prevented during the manufacturing process of the memory device.

Description

트랜지스터 및 그 제조방법Transistor and manufacturing method

제1도는 종래의 MOS트랜지스터 제조방법을 도시한 공정순서도.1 is a process flowchart showing a conventional method for manufacturing a MOS transistor.

제2도는 본 발명에 의한 MOS트랜지스터 제조방법을 도시한 공정순서도.2 is a process flowchart showing a method of manufacturing a MOS transistor according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 반도체 기판 12 : CVD산화막11 semiconductor substrate 12 CVD oxide film

13 : 트렌치 14 : 산화막13: trench 14: oxide film

15 : 게이트전극 16 : 게이트절연막15 gate electrode 16 gate insulating film

17 : 바디층 18 : 소오스 및 드레인영역형성용 마스크17 body layer 18 mask for forming source and drain regions

19 : 소오스 및 드레인영역19 source and drain region

본 발명은 트랜지스터 및 그 제조방법에 관한 것으로, 특히 게이트 브릿지(bridge)예방 및 단차감소에 적당하도록 한 MOS트랜지스터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor and a method for manufacturing the same, and more particularly, to a MOS transistor and a method for manufacturing the same, which are suitable for gate bridge prevention and step reduction.

종래의 MOS트랜지스터 제조방법을 제1도를 참조하여 설명하면, 제1도 (a)와 같이 실리콘기판(1)상에 게이트산화막(2)을 형성하고, 이위에 게이트전극 형성을 위한 도전층으로서, 예컨대 다결정실리콘(3)을 증착한 후, 이위에 CVD산화막(4)을 형성한 다음 게이트전극 패턴형성을 위한 마스크(5)를 적용한 사진식각공정을 통해 상기 CVD 산화막(4)을 패터닝하여 게이트패턴을 형성한 후, 이 CVD산화막패턴을 마스크로 이용하여 상기 다결정실리콘(3)을 식각하여 제1도 (b)에 도시된 바와 같이 게이트전극(3)을 형성한다. 이어서 상기 게이트전극(3)을 이온주입마스크로 이용하여 기판과 반대도전형의 불순물을 선택적으로 이온주입(6)하여 제1도 (c)에 도시된 바와 같이 게이트전극(3) 양단의 기판부위에 소오스 및 드레인영역(7)을 형성함으로써 MOS트랜지스터의 제조를 완료한다.A conventional MOS transistor manufacturing method will be described with reference to FIG. 1, which forms a gate oxide film 2 on a silicon substrate 1 as shown in FIG. 1A, and as a conductive layer for forming a gate electrode thereon. For example, after depositing the polysilicon 3, the CVD oxide film 4 is formed thereon, and then the CVD oxide film 4 is patterned through a photolithography process using a mask 5 for forming a gate electrode pattern. After the pattern is formed, the polysilicon 3 is etched using the CVD oxide film pattern as a mask to form the gate electrode 3 as shown in FIG. Subsequently, using the gate electrode 3 as an ion implantation mask, an ion implantation 6 of impurities of opposite conductivity type to the substrate is selectively carried out, so that the substrate portions of both ends of the gate electrode 3 as shown in FIG. Fabrication of the MOS transistor is completed by forming the source and drain regions 7 in the.

상기한 종래기술에 있어서는 게이트전극 형성으로 인한 단차가 발생하며, 게이트전극 패터닝시 브릿지가 유발될 우려가 있고, 이러한 게이트 브릿지에 의해 소자의 신뢰성이 저하되는 문제가 발생한다.In the above-described prior art, a step may occur due to the formation of a gate electrode, a bridge may be caused when the gate electrode is patterned, and a problem of deterioration of the reliability of the device may be caused by the gate bridge.

본 발명은 상술한 문제를 해결하기 위한 것으로, 게이트 브릿지의 발생을 방지하고 게이트로 인한 단차를 감소시킬 수 있는 MOS트랜지스터 및 그 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide a MOS transistor and a method of manufacturing the same, which can prevent the occurrence of a gate bridge and reduce the step difference caused by the gate.

상기 목적을 달성하기 위한 본 발명의 트랜지스터는 반도체기판과, 상기 반도체기판 소정영역에 형성된 소정의 깊이를 가진 트렌치, 상기 트렌치내에 절연막을 개재하여 매립되어 형성된 게이트전극, 상기 게이트전극 및 기판상부에 형성된 게이트절연막, 및 상기 게이트절연막상부의 게이트전극 양단부위에 각각 형성된 소오스 및 드레인영역으로 이루어진다.A transistor of the present invention for achieving the above object is a semiconductor substrate, a trench having a predetermined depth formed in a predetermined region of the semiconductor substrate, a gate electrode formed by embedding an insulating film in the trench, the gate electrode and formed on the substrate A gate insulating film and a source and drain regions formed on opposite ends of the gate electrode on the gate insulating film, respectively.

상기 목적을 달성하기 위한 본 발명의 트랜지스터 제조방법은 반도체기판 소정부위를 소정깊이로 이방성식각하여 트렌치를 형성하는 단계와, 상기 트렌치 내면에 절연막을 형성하는 단계, 상기 트렌치내에 게이트전극을 형성하는 단계, 상기 게이트전극 표면을 포함한 기판 전면에 게이트절연막을 형성하는 단계, 상기 게이트 절연막상부에 소오스 및 드레인영역 형성을 위한 바디층을 형성하는 단계, 상기 바디층에 선택적으로 불순물을 이온주입하여 상기 게이트전극 양단부위에 소오스 및 드레인영역을 형성하는 단계로 이루어진다.The transistor manufacturing method of the present invention for achieving the above object is anisotropically etching a predetermined portion of the semiconductor substrate to a predetermined depth to form a trench, forming an insulating film on the inner surface of the trench, forming a gate electrode in the trench Forming a gate insulating film on the entire surface of the substrate including the gate electrode surface, forming a body layer on the gate insulating film to form a source and a drain region, and selectively implanting impurities into the body layer to implant the gate electrode. Forming source and drain regions at both ends.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제2도에 본 발명에 의한 MOS트랜지스터의 제조방법을 공정순서에 따라 도시하였다.2 shows a method of manufacturing a MOS transistor according to the present invention according to the process sequence.

먼저, 제2도 (a)에 도시된 바와 같이 반도체기판(11)상에 제1절연막으로서, 예컨대 CVD산화막(12)을 형성한 후, 게이트패턴형성용 마스크(도시하지 않음)를 이용한 사진식각공정을 통해 상기 CVD산화막(12)을 선택적으로 제거하여 게이트가 형성될 부분의 기판영역을 노출시킨 다음, 노출된 기판부위를 소정깊이로 이방성식각하여 트렌치(13)를 형성한다.First, as shown in FIG. 2A, a CVD oxide film 12 is formed as a first insulating film on the semiconductor substrate 11, and then photoetched using a gate pattern forming mask (not shown). By selectively removing the CVD oxide film 12 through the process, the substrate region of the portion where the gate is to be formed is exposed, and then the exposed substrate portion is anisotropically etched to a predetermined depth to form the trench 13.

다음에 제2도 (b)에 도시된 바와 같이 상기 CVD산화막(12)을 제거한 후, 트렌치(13)을 포함한 반도체기판(11) 전면에 제2절연막으로서, 예컨대 얇은 산화막(14)을 형성한 다음 반도체기판(11) 전면에 게이트 형성을 위한 도전층으로서, 예컨대 다결정실리콘을 증착하고 이를 에치백하여 상기 트렌치(13)내에 매립된 형태의 게이트전극(15)을 형성한다.Next, as shown in FIG. 2B, after the CVD oxide film 12 is removed, a thin oxide film 14 is formed on the entire surface of the semiconductor substrate 11 including the trench 13, for example, as a second insulating film. Next, as a conductive layer for forming a gate on the entire surface of the semiconductor substrate 11, for example, polysilicon is deposited and etched back to form a gate electrode 15 embedded in the trench 13.

이어서 제2도 (c)에 도시된 바와 같이 상기 게이트전극(15) 표면을 포함한 반도체기판(11) 전면에 게이트절연막(16)으로서, 예컨대 산화막을 형성하고, 이위에 소오스 및 드레인영역을 위한 바디(body)층(17)으로서, 예컨대 다결정실리콘이나 에피택셜실리콘을 증착한다.Subsequently, as shown in FIG. 2 (c), an oxide film is formed on the entire surface of the semiconductor substrate 11 including the surface of the gate electrode 15, for example, an oxide film, and a body for source and drain regions thereon. As the body layer 17, for example, polycrystalline silicon or epitaxial silicon is deposited.

이어서 상기 바디층(17)상에 소오스 및 드레인영역형성용 마스크(18)를 이용하여 불순물을 상기 바디층(17)에 선택적으로 이온주입(19)하여 제2도 (d)에 도시된 바와 같이 소오스 및 드레인영역(20)을 형성함으로써 MOS트랜지스터를 완성한다.Subsequently, impurities are selectively implanted into the body layer 17 using source and drain region forming masks 18 on the body layer 17, as shown in FIG. The MOS transistor is completed by forming the source and drain regions 20.

이상 상술한 바와 같이 본 발명에 의하면, 트랜지스터의 게이트를 기판내로 매립시켜 형성함으로써 단차를 없앨 수 있게 되므로 다층으로 구성된 공정진행시 유리하다.As described above, according to the present invention, the step of eliminating the step can be eliminated by embedding the gate of the transistor into the substrate, which is advantageous in the progress of a multi-layer process.

또한, 게이트를 기판내부에 형성시킴에 따라서 메모리소자 제조공정시 페일(fail)의 주원인인 워드라인 브릿지를 근본적으로 없앨 수 있으며, 기타 제품의 제조공정시 게이트 브릿지현상을 방지할 수 있다.In addition, since the gate is formed in the substrate, the word line bridge, which is the main cause of the failure in the memory device manufacturing process, can be essentially eliminated, and the gate bridge phenomenon can be prevented during the manufacturing process of other products.

Claims (5)

반도체기판과, 상기 반도체기판 소정영역에 형성된 소정의 깊이를 가진 트렌치, 상기 트렌치내에 절연막을 개재하여 매립되어 형성된 게이트전극, 상기 게이트전극 및 기판상부에 형성된 게이트절연막, 및 상기 게이트절연막상부의 게이트전극 양단부위에 각각 형성된 소오스 및 드레인영역으로 이루어진 것을 특징으로 하는 트랜지스터.A semiconductor substrate, a trench having a predetermined depth formed in the semiconductor substrate predetermined region, a gate electrode formed by embedding an insulating film in the trench, a gate insulating film formed on the gate electrode and the substrate, and a gate electrode on the gate insulating film. A transistor comprising a source and a drain region respectively formed at both ends. 제1항에 있어서, 상기 소오스 및 드레인영역은 상기 게이트절연막 상부에 형성된 바디층의 소정부위에 형성된 불순물영역으로 이루어짐을 특징으로 하는 트랜지스터.The transistor of claim 1, wherein the source and drain regions are formed of an impurity region formed at a predetermined portion of a body layer formed on the gate insulating layer. 제2항에 있어서, 상기 바디층은 다결정실리콘 또는 에피택셜실리콘으로 이루어짐을 특징으로 하는 트랜지스터.3. The transistor of claim 2, wherein the body layer is made of polycrystalline silicon or epitaxial silicon. 반도체기판 소정부위를 소정깊이로 이방성식각하여 트렌치를 형성하는 단계와, 상기 트렌치 내면에 절연막을 형성하는 단계, 상기 트렌치내에 게이트 전극을 형성하는 단계, 상기 게이트전극 표면을 포함한 기판 전면에 게이트절연막을 형성하는 단계, 상기 게이트절연막상부에 소오스 및 드레인영역 형성을 위한 바디층을 형성하는 단계, 상기 바디층에 선택적으로 불순물을 이온주입하여 상기 게이트전극 양단부위에 소오스 및 드레인영역을 형성하는 단계로 이루어진 것을 특징으로 하는 트랜지스터의 제조방법.Forming an trench by anisotropically etching a predetermined portion of the semiconductor substrate to a predetermined depth; forming an insulating film on the inner surface of the trench; forming a gate electrode in the trench; and forming a gate insulating film on the entire surface including the gate electrode surface. Forming a body layer for forming a source and a drain region on the gate insulating layer, and forming a source and a drain region on both ends of the gate electrode by selectively implanting impurities into the body layer. A transistor manufacturing method characterized by the above-mentioned. 제4항에 있어서, 상기 게이트전극을 형성하는 단계는 트렌치를 포함한 기판 전면에 게이트 형성을 위한 도전층을 증착하고 이를 에치백하여 상기 트렌치내에 매립시키는 공정에 의해 행해지는 것을 특징으로 하는 트랜지스터의 제조방법.The method of claim 4, wherein the forming of the gate electrode is performed by depositing a conductive layer for forming a gate on the entire surface of the substrate including the trench, etching the conductive layer, and embedding the conductive layer in the trench. Way.
KR1019940024830A 1994-09-29 1994-09-29 Transistor KR0151190B1 (en)

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