JPWO2022209346A1 - - Google Patents

Info

Publication number
JPWO2022209346A1
JPWO2022209346A1 JP2022529718A JP2022529718A JPWO2022209346A1 JP WO2022209346 A1 JPWO2022209346 A1 JP WO2022209346A1 JP 2022529718 A JP2022529718 A JP 2022529718A JP 2022529718 A JP2022529718 A JP 2022529718A JP WO2022209346 A1 JPWO2022209346 A1 JP WO2022209346A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2022529718A
Other versions
JPWO2022209346A5 (ja
JP7100219B1 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/JP2022/005414 external-priority patent/WO2022209346A1/ja
Priority to JP2022105208A priority Critical patent/JP7177961B2/ja
Application granted granted Critical
Publication of JP7100219B1 publication Critical patent/JP7100219B1/ja
Publication of JPWO2022209346A1 publication Critical patent/JPWO2022209346A1/ja
Publication of JPWO2022209346A5 publication Critical patent/JPWO2022209346A5/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0615Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06152Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry being non uniform, i.e. having a non uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2022529718A 2021-03-29 2022-02-10 半導体装置および半導体モジュール Active JP7100219B1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2022105208A JP7177961B2 (ja) 2021-03-29 2022-06-30 半導体装置および半導体モジュール

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202163167348P 2021-03-29 2021-03-29
US63/167,348 2021-03-29
PCT/JP2022/005414 WO2022209346A1 (ja) 2021-03-29 2022-02-10 半導体装置および半導体モジュール

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2022105208A Division JP7177961B2 (ja) 2021-03-29 2022-06-30 半導体装置および半導体モジュール

Publications (3)

Publication Number Publication Date
JP7100219B1 JP7100219B1 (ja) 2022-07-12
JPWO2022209346A1 true JPWO2022209346A1 (ja) 2022-10-06
JPWO2022209346A5 JPWO2022209346A5 (ja) 2023-02-28

Family

ID=82384804

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2022529718A Active JP7100219B1 (ja) 2021-03-29 2022-02-10 半導体装置および半導体モジュール
JP2022105208A Active JP7177961B2 (ja) 2021-03-29 2022-06-30 半導体装置および半導体モジュール

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2022105208A Active JP7177961B2 (ja) 2021-03-29 2022-06-30 半導体装置および半導体モジュール

Country Status (4)

Country Link
US (2) US20230307393A1 (ja)
JP (2) JP7100219B1 (ja)
KR (1) KR102629278B1 (ja)
CN (1) CN116250088A (ja)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6653740B2 (en) * 2000-02-10 2003-11-25 International Rectifier Corporation Vertical conduction flip-chip device with bump contacts on single surface
JP4270772B2 (ja) * 2001-06-08 2009-06-03 三洋電機株式会社 1チップデュアル型絶縁ゲート型半導体装置
JP6063713B2 (ja) * 2012-11-08 2017-01-18 ルネサスエレクトロニクス株式会社 電池保護システム
JP6598037B2 (ja) * 2015-07-01 2019-10-30 パナソニックIpマネジメント株式会社 半導体装置
JP6795888B2 (ja) * 2016-01-06 2020-12-02 力智電子股▲フン▼有限公司uPI Semiconductor Corp. 半導体装置及びそれを用いた携帯機器
JP6447946B1 (ja) 2018-01-19 2019-01-09 パナソニックIpマネジメント株式会社 半導体装置および半導体モジュール
JP6856569B2 (ja) * 2018-03-21 2021-04-07 株式会社東芝 半導体装置
TWI761740B (zh) * 2018-12-19 2022-04-21 日商新唐科技日本股份有限公司 半導體裝置

Also Published As

Publication number Publication date
KR20230043220A (ko) 2023-03-30
JP7177961B2 (ja) 2022-11-24
US20230307393A1 (en) 2023-09-28
CN116250088A (zh) 2023-06-09
JP2022153382A (ja) 2022-10-12
US20240030167A1 (en) 2024-01-25
JP7100219B1 (ja) 2022-07-12
KR102629278B1 (ko) 2024-01-25

Similar Documents

Publication Publication Date Title
BR112023005462A2 (ja)
BR112023012656A2 (ja)
BR102021015500A2 (ja)
BR112023011738A2 (ja)
BR112023016292A2 (ja)
JPWO2022209346A1 (ja)
BR112023011610A2 (ja)
BR112023011539A2 (ja)
BR112023008976A2 (ja)
BR112023009656A2 (ja)
BR112023006729A2 (ja)
BR102021016837A2 (ja)
BR102021016551A2 (ja)
BR102021016375A2 (ja)
BR102021016176A2 (ja)
BR102021016200A2 (ja)
BR102021015566A2 (ja)
BR102021015450A8 (ja)
BR102021015247A2 (ja)
BR102021015220A2 (ja)
BR102021014056A2 (ja)
BR102021014044A2 (ja)
BR102021013929A2 (ja)
BR102021012571A2 (ja)
BR102021012230A2 (ja)

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220520

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220520

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20220520

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20220614

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20220630

R150 Certificate of patent or registration of utility model

Ref document number: 7100219

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150