JPWO2021172170A1 - - Google Patents
Info
- Publication number
- JPWO2021172170A1 JPWO2021172170A1 JP2022503313A JP2022503313A JPWO2021172170A1 JP WO2021172170 A1 JPWO2021172170 A1 JP WO2021172170A1 JP 2022503313 A JP2022503313 A JP 2022503313A JP 2022503313 A JP2022503313 A JP 2022503313A JP WO2021172170 A1 JPWO2021172170 A1 JP WO2021172170A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
- Debugging And Monitoring (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020033160 | 2020-02-28 | ||
PCT/JP2021/006183 WO2021172170A1 (ja) | 2020-02-28 | 2021-02-18 | ランダムアクセス型メモリ回路及びメモリシステム |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2021172170A1 true JPWO2021172170A1 (ja) | 2021-09-02 |
JPWO2021172170A5 JPWO2021172170A5 (ja) | 2022-10-26 |
Family
ID=77490978
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2022503313A Pending JPWO2021172170A1 (ja) | 2020-02-28 | 2021-02-18 |
Country Status (4)
Country | Link |
---|---|
US (1) | US11978529B2 (ja) |
JP (1) | JPWO2021172170A1 (ja) |
CN (1) | CN115176311A (ja) |
WO (1) | WO2021172170A1 (ja) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4469319B2 (ja) | 2005-06-17 | 2010-05-26 | シャープ株式会社 | 半導体記憶装置 |
US9236102B2 (en) | 2012-10-12 | 2016-01-12 | Micron Technology, Inc. | Apparatuses, circuits, and methods for biasing signal lines |
KR102116671B1 (ko) * | 2014-07-30 | 2020-06-01 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 워드 라인 구동 방법 |
-
2021
- 2021-02-18 CN CN202180016764.8A patent/CN115176311A/zh active Pending
- 2021-02-18 US US17/801,864 patent/US11978529B2/en active Active
- 2021-02-18 JP JP2022503313A patent/JPWO2021172170A1/ja active Pending
- 2021-02-18 WO PCT/JP2021/006183 patent/WO2021172170A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
CN115176311A (zh) | 2022-10-11 |
US20230170005A1 (en) | 2023-06-01 |
WO2021172170A1 (ja) | 2021-09-02 |
KR20220121868A (ko) | 2022-09-01 |
US11978529B2 (en) | 2024-05-07 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220920 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20240119 |