JPWO2019163075A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2019163075A1 JPWO2019163075A1 JP2020501940A JP2020501940A JPWO2019163075A1 JP WO2019163075 A1 JPWO2019163075 A1 JP WO2019163075A1 JP 2020501940 A JP2020501940 A JP 2020501940A JP 2020501940 A JP2020501940 A JP 2020501940A JP WO2019163075 A1 JPWO2019163075 A1 JP WO2019163075A1
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
<装置構成>
図1は、本発明に係る実施の形態1の縦型トレンチMOSFET100の構成を示す平面図であり、縦型トレンチMOSFET100を上方から見た上面図である。図の理解を容易にするため、構造を覆い隠してしまうパッド電極は上面図に記載していない。また、半導体装置の全体像の把握を目的としているため、構造の詳細は記載していない。
本発明に係る実施の形態1の縦型トレンチMOSFET100の製造方法について、図6〜図18を用いて説明する。まず、図6に示す工程において、支持基板には、主面が(0001)面(c面)となった伝導性がn型のGaN基板8を準備し、基板洗浄後、GaN基板8上に有機金属気相エピタキシー(MOVPE)等の手法を用いて、GaN層9、GaN層10、AlxGa1-xN層11、GaN層12およびGaN層13を順次積層する。各GaN層の厚みは、例えばGaN層9が0.5〜3μm、GaN層10が5〜20μm、GaN層12が0.5〜2μm、GaN層13が50〜500nmである。
以上説明した実施の形態1の縦型トレンチMOSFET100においては、オン抵抗を低減するためGaN層16の厚みを5nm〜10nmと薄くしているが、GaN層16の厚みを薄くした場合に、トレンチゲート4側面の結晶ダメージおよびトレンチゲート4側面からの不純物の混入に起因して、チャネル層の結晶品質を高めにくい場合がある。このような場合には、GaN層16の厚みを厚く形成した後に、ICP−RIE装置等を用いたエッチバックを行い、トレンチゲート4底部のGaN層16を選択的に除去しても良い。
<装置構成>
図21は、本発明に係る実施の形態2の縦型トレンチMOSFET200のソース・ユニットセルを示す断面図である。図21に示すように、縦型トレンチMOSFET200は、図2を用いて説明した縦型トレンチMOSFET100とほぼ同じ構造を有しており、縦型トレンチMOSFET100と同一の構成については同一の符号を付し、重複する説明は省略する。
本発明に係る実施の形態2の縦型トレンチMOSFET200の製造方法について、図23〜図29を用いて説明する。
以上説明した本発明に係る実施の形態1および2以外にも種々の実施の形態が考えられる。
また、異種の自立基板を用いる場合は、上記以外の手法として擬似縦型構造と呼ばれる構造を採ることもできる。図31には擬似縦型構造の一例として縦型トレンチMOSFET400の断面図を示している。図31では、擬似縦型構造の特徴を端的に表すターミネーションセルの断面図を示している。
Claims (19)
- 第1主面および第2主面を有した支持基板と、
前記支持基板の前記第1主面側に設けられた第1導電型の第1GaN層と、
前記第1GaN層上に設けられた第1導電型の第2GaN層と、
前記第2GaN層上に設けられたAlxGa1−xN(0<x<1)層と、
前記AlxGa1−xN(0<x<1)層上に設けられた第2導電型の第3GaN層と、
前記第3GaN層上に設けられた第1導電型の第4GaN層と、
少なくとも前記第4GaN層上を覆う絶縁膜と、
前記第4GaN層の上面から前記第2GaN層内に達するトレンチゲートと、
前記トレンチゲート内にゲート絶縁膜を介して設けられたゲート電極と、
前記第3GaN層に接続された第1主電極と、
前記第1主電極と対をなす第2主電極と、を備え、
前記第3のGaN層のドナー濃度は、前記第4GaN層のドナー濃度よりも低い、半導体装置。 - 前記AlxGa1-xN(0<x<1)層は、
5〜40nmの厚みを有し、
Al組成はxが0.15〜0.35である、請求項1記載の半導体装置。 - 前記第1主電極は、
前記第4GaN層を厚さ方向に貫通して前記第3のGaN層内に達するコンタクト部を介して前記第3GaN層に接続される、請求項1記載の半導体装置。 - 前記ゲート絶縁膜は、少なくともSiO2膜を含む多層膜で構成される、請求項1記載の半導体装置。
- 前記ゲート電極は、少なくともTiN膜または多結晶シリコン膜を含む、請求項1記載の半導体装置。
- 第2GaN層、前記第3GaN層、前記AlxGa1−xN(0<x<1)層および前記第4GaN層はメサ構造を構成し、
前記メサ構造の側面部は、順テーパ型に傾斜し、前記側面部に連続する底面部は、前記第2GaN層で構成され、
前記絶縁膜は、
前記メサ構造の前記側面部および前記底面部を覆う、請求項1記載の半導体装置。 - 前記メサ構造の前記底面部の前記支持基板からの高さ位置は、前記トレンチゲートの底面よりも下に位置する、請求項6記載の半導体装置。
- 前記絶縁膜は、
シリコンを含むシロキサン樹脂膜を含む、請求項6記載の半導体装置。 - 前記第1主電極はパッド電極に電気的に接続され、
前記絶縁膜は、
前記メサ構造の前記側面部から前記底面部にかけて段階的に厚くなるように設けられ、
前記パッド電極は、
前記絶縁膜を介して前記側面部および前記底面部の上を覆い、前記底面部上において終端部を有する、請求項8記載の半導体装置。 - 前記トレンチゲートは、
前記第4GaN層、前記第3GaN層および前記AlxGa1−xN(0<x<1)層を厚さ方向に貫通して前記第2GaN層内に達し、その側面は、前記第4GaN層、前記第3GaN層および前記AlxGa1−xN(0<x<1)層の端面を含み、
少なくとも前記トレンチゲートの側面に接して設けられ、前記第3GaN層よりも不純物濃度が低い第2導電型の第5GaN層をさらに備える、請求項1記載の半導体装置。 - 前記第5GaN層は、
5〜10nmの厚みを有する、請求項10記載の半導体装置。 - 前記第5GaN層は、
前記トレンチゲートの側面のみに接して設けられる、請求項10記載の半導体装置。 - 前記トレンチゲートは、
前記第4GaN層および前記第3GaN層を厚さ方向に貫通して前記第2GaN層内に達し、その側面は、前記第4GaN層および前記第3GaN層の端面を含み、
前記AlxGa1−xN(0<x<1)層の端面と、前記トレンチゲートの側面との間に前記第3GaN層が介在し、
前記ゲート絶縁膜は、
前記トレンチゲートの内面に接して設けられる、請求項1記載の半導体装置。 - 前記支持基板は、
第1導電型のGaN基板、Si基板、サファイア基板および炭化シリコン基板の何れかを含み、
前記第2主電極は、前記支持基板の第2主面上に配置される、請求項1記載の半導体装置。 - 前記支持基板は、AlN基板、Si基板およびサファイア基板の何れかを含み、
前記AlN基板、Si基板およびサファイア基板の何れかは、
前記第1主面から前記第2主面にかけて前記AlN基板、Si基板およびサファイア基板の何れかを貫通する複数のビアホールを有し、
前記複数のビアホール内には、導体膜が埋め込まれ、前記第2主電極は、前記支持基板の前記第2主面上に配置され、前記導体膜を介して前記第1GaN層と電気的に接続される、請求項1記載の半導体装置。 - 前記支持基板は、AlN基板、Si基板およびサファイア基板の何れかを含み、
前記第1GaN層は、
前記AlN基板、Si基板およびサファイア基板の何れかの基板端まで延在するように設けられ、
前記絶縁膜は、
前記基板端を覆い、前記基板端において、前記絶縁膜を貫通して設けられた開口部の底部に前記第1GaN層が露出し、
前記第2主電極は、
前記開口部内に埋め込まれて前記第1GaN層に接すると共に、前記絶縁膜の上部に延在するように設けられる、請求項1記載の半導体装置。 - 前記第3GaN層は、
第2導電型の不純物としてMgを含み、Mgの濃度が1×1017cm−3以下であり、かつ前記第3GaN層の水平方向の長さを規定するトレンチ間距離が100nm以下である、請求項1記載の半導体装置。 - 前記ゲート電極は、
ゲートセルにおいてゲートパッド電極と電気的に接続され、
前記ゲート電極と前記ゲートパッド電極との間に設けられたAuで構成される保護電極をさらに備える、請求項1記載の半導体装置。 - 前記AlxGa1−xN(0<x<1)層は、その底面の前記支持基板からの高さ位置が、前記ゲート電極の底面と同じ、または前記ゲート電極の底面よりも上に位置する、請求項1記載の半導体装置。
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