JPWO2019017104A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JPWO2019017104A1 JPWO2019017104A1 JP2019530926A JP2019530926A JPWO2019017104A1 JP WO2019017104 A1 JPWO2019017104 A1 JP WO2019017104A1 JP 2019530926 A JP2019530926 A JP 2019530926A JP 2019530926 A JP2019530926 A JP 2019530926A JP WO2019017104 A1 JPWO2019017104 A1 JP WO2019017104A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 244
- 239000000758 substrate Substances 0.000 claims description 26
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- 238000001514 detection method Methods 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 229910052721 tungsten Inorganic materials 0.000 description 1
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Abstract
Description
実施の形態1にかかる半導体装置の構造について説明する。図1は、実施の形態1にかかる半導体装置の平面レイアウトを示す平面図である。平面レイアウトとは、チップおもて面(半導体チップ(半導体基板)10のおもて面)から見た各部の平面形状および配置構成である。図1では、IGBT領域1およびFWD領域2にそれぞれ配置されるIGBTおよびFWDの素子構造を図示省略する。また、図1には、略長方形状の平面形状の半導体チップ10を示すが(図8〜10においても同様)、半導体チップ10の平面形状は正方形状であってもよい。
次に、実施の形態2にかかる半導体装置の構造について説明する。図7は、実施の形態2にかかる半導体装置の平面レイアウトを示す平面図である。実施の形態2にかかる半導体装置が実施の形態1に係る半導体装置と異なる点は、FWD領域2の長さL2を短くした点である。図7(a)には、第1方向XにFWD領域2同士が対向して配置された状態を示している。図7(b)は、実施の形態1と同様に、第1方向XにFWD領域2同士が対向しないように配置された状態を示している。
次に、実施の形態3にかかる半導体装置の構造について説明する。図8は、実施の形態3にかかる半導体装置の平面レイアウトを示す平面図である。実施の形態3にかかる半導体装置は、電流の検出・制御を行うためのIGBT(センスIGBT)に実施の形態1にかかる半導体装置を適用したものである。
次に、実施の形態4にかかる半導体装置の構造について説明する。図9は、実施の形態4にかかる半導体装置の平面レイアウトを示す平面図である。実施の形態4にかかる半導体装置が実施の形態3にかかる半導体装置と異なる点は、各FWD領域72の幅w1を狭くして、各FWD領域72の放熱性を向上させた点である。各FWD領域72の幅w1を狭くした分、例えば、FWD領域72の個数を増やすことで、FWD領域72の総表面積を所定の大きさ(例えば従来構造のFWD領域102の総表面積と同程度)で維持することができる。
次に、実施の形態5にかかる半導体装置の構造について説明する。図10は、実施の形態5にかかる半導体装置の平面レイアウトを示す平面図である。実施の形態5にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、活性領域11の一方の辺11a側のFWD領域82の一部と、他方の辺11b側のFWD領域82の一部とが、第2方向Yに対向する点である。IGBT領域81は、実施の形態1と同様に、活性領域11の、FWD領域82以外の領域である。
1a IGBT領域の、活性領域の一方の辺側のFWD領域間に挟まれた部分
1b IGBT領域の、活性領域の他方の辺側のFWD領域間に挟まれた部分
2,72,82 FWD領域
3 ゲートパッド
10 半導体チップ
11 活性領域
11a〜11d 活性領域の辺
11e 活性領域の中央部
12 エッジ終端領域
13 活性領域の中央部側におけるIGBT領域とFWD領域との境界付近
14 活性領域とエッジ終端領域との境界付近
15 IGBT領域とFWD領域との境界領域
16 IGBT領域とFWD領域との境界
21 IGBT領域
31 第1ゲートトレンチ
32 第2ゲートトレンチ
33 p+型コンタクト領域
34a〜34c コンタクトホール
35 ポリシリコン層
36 ゲートランナー
41 n-型ドリフト領域
42 p型ベース領域
43 n+型エミッタ領域
44 p+型コンタクト領域
45 n型CS領域
46 第1ゲート絶縁膜
47 ゲート電位の第1ゲート電極
48 第2ゲート絶縁膜
49 エミッタ電位の第2ゲート電極
50 層間絶縁膜
51 おもて面電極
52 n型FS領域
53 p+型コレクタ領域
54 n+型カソード領域
55 裏面電極
61 p型ウェル領域
62 p型ウェル領域
73 ゲートパッド
74 アノードパッド
75 カソードパッド
76 OCパッド
77 OVパッド
D1 IGBT領域のうち、第1方向Xに対して斜めの方向に離れた部分間の距離
D2 第1方向Xに対して斜めの方向に離れたFWD領域間の距離
X FWD領域がストライプ状に延びる方向(第1方向)
Y FWD領域がストライプ状に延びる方向と直交する方向(第2方向)
Z 深さ方向
w1 FWD領域の幅
w2 第2方向に隣り合うFWD領域間の幅
w3 隣り合う第1ゲートトレンチ間の幅(メサ幅)
w4 第1方向における第1,2ゲートトレンチ間の幅
w5 FWD領域の他方の辺側の端部と当該他方の辺との間の距離
S IGBT領域の幅
Claims (16)
- 半導体基板に設けられた、電流が流れる活性領域と、
前記活性領域に設けられ、第1のトレンチゲート構造を有する第1素子が配置された第1素子領域と、
前記活性領域に設けられ、第2のトレンチゲート構造を有する第2素子が配置された第2素子領域と、
を備え、
前記第1のトレンチゲート構造は、
前記半導体基板の第1主面側に設けられた第1トレンチと、
前記第1トレンチの内部に第1ゲート絶縁膜を介して設けられた第1ゲート電極と、を有し、
前記第2のトレンチゲート構造は、
前記半導体基板の第1主面側に、前記第1トレンチと離して設けられた第2トレンチと、
前記第2トレンチの内部に第2ゲート絶縁膜を介して設けられた第2ゲート電極と、を有し、
前記第2素子領域は、互いに離して複数配置され、
前記第1素子領域は、複数の前記第2素子領域の間に挟まれた連続した領域であることを特徴とする半導体装置。 - 前記第2素子領域は、前記活性領域の外周寄りに配置されていることを特徴とする請求項1に記載の半導体装置。
- 複数の前記第2素子領域は、前記半導体基板の第1主面に平行で、かつ矩形状の平面形状を有する前記活性領域の外周を構成する1組の対辺それぞれからもう1組の対辺に平行な第1方向に延びるストライプ状のレイアウトに配置されており、
前記活性領域の前記第1方向に対向する1組の対辺のうち、一方の辺側に配置された前記第2素子領域と、他方の辺側に配置された前記第2素子領域と、は前記第1方向と直交する第2方向に互い違いに配置され、かつ本数を同数とすることを特徴とする請求項1に記載の半導体装置。 - 前記第2素子領域の前記第1方向の長さは、前記第2素子領域の前記第2方向の幅よりも長いことを特徴とする請求項3に記載の半導体装置。
- 隣り合う前記第2素子領域の間の幅は、前記第2素子領域の前記第2方向の幅以上であることを特徴とする請求項3に記載の半導体装置。
- 前記第2素子領域の前記第2方向の幅は、50μm以上であることを特徴とする請求項3に記載の半導体装置。
- 前記第1素子は、
前記半導体基板に設けられた第1導電型の第1半導体領域と、
前記半導体基板の第1主面の表面層に、前記第1半導体領域に接して設けられた第2導電型の第2半導体領域と、
前記第2半導体領域の内部に選択的に設けられた第1導電型の第3半導体領域と、
前記第3半導体領域および前記第2半導体領域を貫通して前記第1半導体領域に達する前記第1トレンチと、
前記第1ゲート電極と、
前記半導体基板の第2主面の表面層に、前記第1半導体領域に接して設けられた第2導電型の第4半導体領域と、
前記第2半導体領域および前記第3半導体領域に接する第1電極と、
前記第4半導体領域に接する第2電極と、を有し、
前記第2素子は、
前記第1素子領域から前記第2素子領域に延在する前記第1半導体領域および前記第2半導体領域と、
前記第2半導体領域を貫通して前記第1半導体領域に達する前記第2トレンチと、
前記第2ゲート電極と、
前記半導体基板の第2主面の表面層に、前記第1半導体領域および前記第4半導体領域に接して設けられた第1導電型の第5半導体領域と、
前記第2半導体領域に接する前記第1電極と、
前記第5半導体領域に接する前記第2電極と、を有することを特徴とする請求項3に記載の半導体装置。 - 前記第1トレンチは、前記半導体基板の第1主面に平行な方向で、かつ前記第1方向に延びるストライプ状のレイアウトに配置され、
前記第2トレンチは、前記半導体基板の第1主面に平行な方向で、かつ前記第1方向に延びるストライプ状のレイアウトに配置され、
前記第1トレンチと前記第2トレンチとは、前記第1方向に端部同士が対向し、
前記第1トレンチと前記第2トレンチとの端部間に設けられ、前記第1トレンチの端部および前記第2トレンチとの端部に接する第2導電型の第6半導体領域をさらに備えることを特徴とする請求項3に記載の半導体装置。 - 前記第1トレンチは、前記半導体基板の第1主面に平行な方向で、かつ前記第1方向に延びるストライプ状のレイアウトに配置され、
前記第2トレンチは、前記半導体基板の第1主面に平行な方向で、かつ前記第1方向に延びるストライプ状のレイアウトに配置され、
前記第1トレンチと前記第2トレンチとは、前記第1方向に端部同士が対向し、
前記第1トレンチと前記第2トレンチとの端部間に設けられ、前記第1トレンチの端部および前記第2トレンチとの端部に接する第2導電型の第6半導体領域をさらに備えることを特徴とする請求項7に記載の半導体装置。 - 前記第6半導体領域の深さは、前記第1トレンチの深さおよび前記第2トレンチの深さよりも深いことを特徴とする請求項8に記載の半導体装置。
- 前記第1素子領域と前記第2素子領域との間に境界領域をさらに備え、
前記境界領域には、
前記第1半導体領域の表面層に前記第2半導体領域が配置されていることを特徴とする請求項7に記載の半導体装置。 - 前記境界領域の前記第2半導体領域に、
前記第2半導体領域の表面層に配置された、前記第2半導体領域よりも不純物濃度の高い第2導電型の第7半導体領域と、
前記第2半導体領域の下面に配置された、前記第1半導体領域よりも不純物濃度の高い第1導電型の第8半導体領域と、を備えることを特徴とする請求項11に記載の半導体装置。 - 前記第7半導体領域は、前記第2ゲート電極と電気的に接続されていることを特徴とする請求項12に記載の半導体装置。
- 前記第1素子領域と前記第2素子領域との間に境界領域をさらに備え、
前記境界領域に、
前記第1半導体領域の表面層に設けられ、前記第1トレンチおよび前記第2トレンチの底部を覆う前記第6半導体領域と、
前記第6半導体領域の表面層に設けられた、前記第6半導体領域よりも不純物濃度の高い第2導電型の第9半導体領域と、備えることを特徴とする請求項9に記載の半導体装置。 - 前記第9半導体領域は、前記第2ゲート電極と電気的に接続されていることを特徴とする請求項14に記載の半導体装置。
- 前記第1素子領域は絶縁ゲート型バイポーラトランジスタであり、
前記第2素子領域は還流ダイオードであることを特徴とする請求項1〜15のいずれか一つに記載の半導体装置。
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