JPWO2018163005A1 - タッチパネルシステム、電子機器および半導体装置 - Google Patents
タッチパネルシステム、電子機器および半導体装置 Download PDFInfo
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- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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Abstract
Description
本実施の形態は、本発明の一形態であるタッチパネルシステムとそれを用いた電子機器について説明を行う。なお、本実施の形態では電子機器の例として情報端末について説明を行う。
本実施の形態は、本発明の一形態であるタッチパネルシステムとそれを用いた電子機器について説明を行う。なお、本実施の形態では電子機器の例として受像装置について説明を行う。
本実施の形態では、ニューラルネットワークの演算に用いることが可能な、アナログ積和演算回路について説明する。
本実施の形態は、上記実施の形態に示すOSメモリを用いたアナログ積和演算回路(OS−APS)の具体例について、図14乃至図18を用いて説明する。本実施の形態は実施の形態3に示すアナログ積和演算回路とは異なる例について説明を行う。なお、本実施の形態において、ゲートは特に断りの無い場合はフロントゲートを指すものとする。
図14は、APS(アナログ積和演算回路)100の構成の例を示す図である。APS100は、電流源回路130、メモリセルアレイ120およびオフセット回路110を有する。
次に、図15を用いて、APS100が有するメモリセルアレイ120の構成の例を示す。メモリセルアレイ120はアナログメモリとして機能することができる。ただしメモリセルアレイ120は図15の構成に限らない。アナログメモリとして機能できる回路構成であれば、その他の構成であってもよい。
次に、図16を用いて、APS100が有する電流源回路130の構成の例を示す。
APS100が有する電流源回路130は、図16の構成に限られない。たとえばpチャネルトランジスタを用いて電流源回路130を構成してもよい。図17に、pチャネルトランジスタを用いた電流源回路130の構成例を示す。
次に、メモリセルアレイ120に図15の構成、電流源回路130に図16の構成を採用した場合の図14に示すAPS100の動作の例を、図18のタイミングチャートを用いて説明する。
I0[i,j]=k(VPR−VX[i,j]−Vth)2 式(1)
となる。また、参照メモリセルREF[i]におけるトランジスタ124に流れる電流(吸い込む電流)IREF0[i]は、
IREF0[i]=k(VPR−Vth)2 式(2)
となる。ここで、kは係数、Vthはトランジスタ124の閾値電圧である。
ICREF−ICM0=ΣIREF0[i] 式(3)
が成り立つようにトランジスタ138のゲート電位が設定される。ここで、トランジスタ134とトランジスタ138とはカレントミラーを構成するため、トランジスタ134にも電流ICM0が流れる。
IC[j]−ICM0−ΣI0[i,j]=IOF[j] 式(4)
が成り立つ。
I[i,j]=k(VPR−VX[i,j]+VW[i]−Vth)2 式(5)
となる。また、参照メモリセルREF[i]におけるトランジスタ124に流れる電流(吸い込む電流)IREF[i]は、
IREF[i]=k(VPR+VW[i]−Vth)2 式(6)
となる。
ICREF−ICM=ΣIREF[i] 式(7)
が成り立つように、トランジスタ138のゲート電位が設定される。ここで、トランジスタ134とトランジスタ138とはカレントミラーを構成するため、トランジスタ134にも電流ICMが流れる。
ΔI[j]
=(IC[j]−ICM−ΣI[i,j])−(IC[j]−ICM0−ΣI0[i,j])
=ΣIREF[i]−ICREF−ΣI[i,j]+ICREF−ΣIREF0[i]+ΣI0[i,j]
=Σk(VPR+VW[i]−Vth)2−Σk(VPR−VX[i,j]+VW[i]−Vth)2−Σk(VPR−Vth)2+Σk(VPR−VX[i,j]−Vth)2
=2kΣ(VW[i]・VX[i,j]) 式(8)
ここで、Σ(VW[i]・VX[i,j])は、第1のアナログデータに対応する電位VX[i,j]と、第2のアナログデータに対応する電位VW[i]と、の積の和に相当する。つまり、第1のアナログデータと第2のアナログデータとの積和値を算出することができることになる。
本実施の形態は、実施の形態1に示す表示パネル20の詳細について説明を行う。
まず、図3の画素14に用いることができる回路構成について、図19を用いて説明を行う。
次に、表示パネル20の構成例について、図20および図21の断面図を用いて説明する。
作製工程中の熱処理に耐えうる程度の耐熱性を有する材料を基板4001等に用いることができる。例えば、厚さ0.7mm以下0.1mm以上の材料を基板4001に用いることができる。具体的には、厚さ0.1mm程度まで研磨した材料を用いることができる。
例えば、基板4001に用いることができる材料を基板4006に用いることができる。例えば、基板4001に用いることができる材料から選択された透光性を備える材料を、基板4006に用いることができる。または、片側の表面に、例えば1μm以下の反射防止膜が形成された材料を基板4006に用いることができる。具体的には、誘電体を3層以上、好ましくは5層以上、より好ましくは15層以上積層した材料を基板4006に用いることができる。これにより、反射率を0.5%以下好ましくは0.08%以下に抑制することができる。または、基板4001に用いることができる材料から選択された複屈折が抑制された材料を、基板4006に用いることができる。
1a 情報端末
2 表示部
2a 表示部
3a 筐体
3b 筐体
3c 筐体
4 ヒンジ
5 サーバー
10 タッチパネルシステム
11 画素部
12 ゲートドライバ
13 ソースドライバ
14 画素
15 タッチセンサ
16 センシング回路
19 NN回路
20 表示パネル
21 ゲート線
22 ソース線
25 ホスト
31 入力層
32 中間層
33 出力層
41_1 ニューロン
41_2 ニューロン
41_3 ニューロン
42_1 ニューロン
42_2 ニューロン
42_3 ニューロン
43_1 ニューロン
43_2 ニューロン
43_3 ニューロン
50 APS
51 メモリセルアレイ
52 回路
53 回路
54 回路
60 受像装置
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62 入力領域
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64 アンテナ
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70 タッチパネルシステム
72 エンコーダ
73 画像処理回路
74 デコーダ
75 アナログフロントエンド
76 受信回路
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81 上部カバー
82 FPC
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84 FPC
87 バックライトユニット
88 光源
89 フレーム
90 プリント基板
91 バッテリー
92 下部カバー
100 APS
110 オフセット回路
111 トランジスタ
112 トランジスタ
113 トランジスタ
114 容量素子
115 抵抗素子
120 メモリセルアレイ
123 トランジスタ
124 トランジスタ
125 容量素子
130 電流源回路
131a 定電流回路
131b 定電流回路
132 トランジスタ
133 トランジスタ
134 トランジスタ
135 容量素子
136 トランジスタ
137 トランジスタ
138 トランジスタ
139 容量素子
140 トランジスタ
141 トランジスタ
510 電極
511 電極
512 半導体層
516 電極
517 電極
3125 発光素子
3232 トランジスタ
3233 容量素子
3431 トランジスタ
3432 液晶素子
3435 ノード
3436 ノード
3437 ノード
4001 基板
4005 シール材
4006 基板
4008 液晶層
4014 配線
4015 電極
4018 FPC
4019 異方性導電層
4021 電極
4030 電極層
4031 電極層
4032 絶縁層
4033 絶縁層
4035 スペーサ
4102 絶縁層
4103 絶縁層
4110 絶縁層
4111 絶縁層
4112 絶縁層
4510 隔壁
4511 発光層
4514 充填材
5001 フレキシブルタッチパネル
5002 筐体
5003 手書き文字
Claims (4)
- 第1の回路と、表示部と、タッチセンサと、を含む電子機器であって、
前記第1の回路は、ニューラルネットワークを有し、
前記表示部は、フレキシブルディスプレイを有し、
前記タッチセンサは、入力された手書き文字を画像情報として、前記第1の回路に出力する機能を有し、
前記第1の回路は、前記画像情報を解析し、文字情報に変換する機能と、前記文字情報を含む画像を前記表示部に表示させる機能とを有し、
前記解析は、前記ニューラルネットワークを用いた推論により行われることを特徴とする、
電子機器。 - 第1の筐体、第2の筐体、第3の筐体、複数のヒンジ、第1の回路、表示部、タッチセンサを含み、
前記第1の回路は、ニューラルネットワークを有し、
前記表示部は、フレキシブルディスプレイを有し、
前記フレキシブルディスプレイは、前記第1の筐体、前記第2の筐体、及び前記第3の筐体のそれぞれに保持される部分を有し、
前記タッチセンサは、入力された手書き文字を画像情報として、前記第1の回路に出力する機能を有し、
前記第1の回路は、前記画像情報を解析し、文字情報に変換する機能と、前記文字情報を含む画像を前記表示部に表示させる機能とを有し、
前記解析は、前記ニューラルネットワークを用いた推論により行われ、
前記第1の筐体、前記第2の筐体、及び前記第3の筐体は、前記フレキシブルディスプレイが開いた状態と、3つに折り畳まれた状態との間で可逆的に変形するように、前記複数のヒンジによって連結されている、
電子機器。 - 請求項1または請求項2において、
前記第1の回路は、アナログデータを保持することが可能なメモリを含む、
電子機器。 - 請求項1または請求項2において、
前記第1の回路は、チャネル形成領域に金属酸化物を含むトランジスタを含む、
電子機器。
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JP2022183317A JP7394197B2 (ja) | 2017-03-10 | 2022-11-16 | 電子機器 |
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JP2022183317A Active JP7394197B2 (ja) | 2017-03-10 | 2022-11-16 | 電子機器 |
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JP2023029840A (ja) | 2023-03-07 |
WO2018163005A1 (ja) | 2018-09-13 |
US11610544B2 (en) | 2023-03-21 |
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US20200004357A1 (en) | 2020-01-02 |
JP2024035238A (ja) | 2024-03-13 |
US20220172677A1 (en) | 2022-06-02 |
US11227543B2 (en) | 2022-01-18 |
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