JPWO2007013367A1 - 半導体素子及び電気機器 - Google Patents
半導体素子及び電気機器 Download PDFInfo
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- JPWO2007013367A1 JPWO2007013367A1 JP2007528435A JP2007528435A JPWO2007013367A1 JP WO2007013367 A1 JPWO2007013367 A1 JP WO2007013367A1 JP 2007528435 A JP2007528435 A JP 2007528435A JP 2007528435 A JP2007528435 A JP 2007528435A JP WO2007013367 A1 JPWO2007013367 A1 JP WO2007013367A1
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Abstract
Description
しかし、スイッチング素子21やダイオード22の応答速度が有限であるため、スイッチング素子21やダイオード22に対してオン状態からオフ状態に切り替える信号を与えても、すぐにはオフ状態とならない。このため、上アーム23Hと下アーム23Lとのオン、オフの切り替えを同時に行うと、上アーム23Hと下アーム23Lとが共にオン状態となり得る。このような状態は、高電位25とアース電位24とがショートした状態であり、インバータ回路に大電流が流れてしまう。また、この電流は損失電流となるため、スイッチング損失が増加し、電力利用効率を低下させる。そして、インバータ回路においては高速のスイッチングによる高効率インバータ制御を行うため、一回のスイッチング損失がスイッチング回数分積算されて、全体のスイッチング損失が大きくなる。そこで、従来においては、スイッチング素子21やダイオード22の応答速度を考慮してスイッチングのタイミングを決めている。換言すると、スイッチング素子21やダイオード22の応答速度の制約により、インバータ制御の周波数が決められている。しかし、さらに高速なスイッチングにより高効率インバータ制御をしようとする場合には、スイッチング素子21及びダイオード22のスイッチングをさらに高速化することが求められる。
一方、ダイオードのスイッチングを高速化したものには、キャリアのライフタイム制御を施したファーストリカバリーダイオードがある。しかし、ファーストリカバリーダイオードは、数10kHz以上の高周波での動作が困難である。また、ファーストリカバリーダイオードはバイポーラデバイスであるため、マイノリティーキャリアの拡散によってオン抵抗は小さくなるが、マイノリティーキャリアのライフタイムが長いため、オンからオフへのスイッチングに時間がかかる。また、ダイオードのスイッチングをさらに高速化したものに、ショットキー電極を半導体にショットキー接触させたショットキーダイオードがある。ショットキーダイオードはユニポーラデバイスであり、マイノリティーキャリアの影響を受けないため、オンからオフへのスイッチングを高速に行うことができる。しかし、シリコンにより構成されたショットキーダイオードの場合には、100V程度の耐圧しかなく、600V以上の耐圧を必要とするパワーエレクトロニクス分野では利用できなかった。
例えば、スイッチング素子のターンオフ時にインダクタンス負荷により発生する逆起電力としてのプラス電圧が、ソース電極に印加された場合には、寄生ダイオードを介して少数キャリアとしての正孔がn型領域に注入され、ダイオード動作の逆回復時間の遅れをきたすことになる。
一方、縦型MOSFETをワイドバンドギャップ半導体により構成し、この縦型MOSFETのドリフト領域にショットキー接合するようにショットキー電極を配設することによって、ショットキーダイオードとスイッチング素子たるMOSFETとをワンチップとして集積することができるようになる(特許文献1参照)。
本発明は、このような事情に鑑みてなされたものであり、高速スイッチング動作とエネルギー損失低減との両立が図れ、かつ電気機器のインダクタンス負荷等による逆起電力に基づく電流集中耐性に優れた半導体素子及び電気機器を提供することを目的とする。
また、本件発明者らは、半導体素子端部に電界が集中してそこが破壊されることも原因の1つであることを発見した。すなわち、縦型MOSFETでは、オフ状態においてドレイン電極とソース電極との間に電圧を印加すると、その電圧が、ドリフト領域とこれに接するチャネル領域を含むウェルとの間のp/n接合の空乏層に実質的に印加され、その電界はp/n接合において最大になる。一方、特許文献1の構成では、半導体素子が多数のセルを有し、その多数のセルに電界効果トランジスタがそれぞれ形成され、互いに並列接続されている。このような構成では、上記セルが配列された領域中では、p/n接合の電界はほぼ一様であるが、この領域の端において、p/n接合の電界が電界集中により大きくなる。このため、半導体素子の端部に、例えば、メサ構造、ガードリング(フィールドリミッティングリング構造)などを付加している。このような構造を付加すると、当該部分における電界集中が抑制され、その結果、耐圧が向上する。しかし、サージ電圧が印加された場合には、半導体素子の端部における電界が大きくなり、そこが破壊される場合があった。
前記半導体層の上面に、平面視において前記ダイオード形成領域と前記半導体層の端との間に位置するように、ガードリングが形成されていてもよい。
また、本発明は、交流駆動装置のインバータ電源回路を構成する半導体素子として用いることができ、例えば、前記半導体素子がアームモジュールとして組み込まれている電気機器に適用することができる。
前記交流駆動装置の一例は、前記インバータ電源回路により駆動される交流モータであり、この交流モータにより、例えばエアコンディショナーのコンプレッサが駆動される。
本発明の上記目的、他の目的、特徴、及び利点は、添付図面参照の下、以下の好適な実施態様の詳細な説明から明らかにされる。
2 半導体基板
3 半導体層(SiC層)
3a ドリフト領域
4 p型半導体領域(第2導電型領域)
4a p型半導体領域外周部
4b p型半導体領域中央部
5 ソース領域
6 ソース電極
7 ゲート絶縁膜
8 ゲート電極
9 ダイオード形成領域
9a,9b ショットキー電極
10 トランジスタ形成領域
11 ガードリング(耐圧部材)
12 ボンディングパッド
12S ソース・ショットキー用パッド
12G ゲート用パッド
13S、13G ワイヤ
14 半導体素子端部
15 ドレイン電極端子
16 ソース電極端子
17 ゲート電極端子
18 封止樹脂
20 半導体素子
21 スイッチング素子
22 ダイオード
23 相スイッチング回路
23H 上アーム
23L 下アーム
24 アース電位配線(アース電位)
25 高電位配線(高電位)
26 アームの中点
27 モータ入力端子
28 三相モータ
50 仮想の境界線
50a,50c 横境界ライン
50b,50d,50f 縦境界ライン
50X X部分仮想線
50Y Y部分仮想線
51 ジグザグライン
70 ショットキーダイオード
80 ダイオードセル
90 電界効果トランジスタ(MOSFET)
100 トランジスタセル
200 セル
201 セル形成領域
図1は、本発明の第1実施形態の半導体素子の構成を示す平面図である。図2は、図1の半導体素子の構成の一部を拡大した部分平面図である。図3は、図1の半導体素子の断面視における構造を示す部分断面図であって、図2に示すIII−III線に沿って切断した断面図である。
図1及び図2に示すように、本実施形態の半導体素子20は、セル形成領域201を有している。このセル形成領域201は、ここでは、平面視において正方形である。なお、セル形成領域201は、平面視において正方形である場合に限られない。このセル形成領域201は、平面視において格子状の仮想の境界線50で区切られた複数のセル200、言い換えれば、行列状に区画された領域からなる複数のセル200に分割されている。各セル200は、ここでは正方形である。この複数のセル200は、後述する電界効果トランジスタ90が形成されたトランジスタセル100と、ショットキー電極9aが配設されショットキーダイオード70が形成されたダイオードセル80とで構成される。
図1及び図2において、2点鎖線で示した仮想の境界線50は、請求の範囲や明細書の内容を説明しやすくするものであって、本発明を具現化した製品に実在するものではない。仮想の境界線50は、トランジスタセル100同士が隣接する場合には、トランジスタセル100の各々の中心から等距離に縦方向又は横方向に延びる仮想線であり、ダイオードセル80同士が隣接する場合にはダイオードセル80の各々の中心から等距離に縦方向又は横方向に延びる仮想線であり、トランジスタセル100とダイオードセル80とが隣接する場合にはトランジスタセル100の中心とダイオードセル80の中心とから等距離に縦方向又は横方向に延びる仮想線である。仮想の境界線50は、電界効果トランジスタ90及びショットキーダイオード70の形状により、適宜、変更される。
また、図9(a)中の左端における列方向の仮想線50dは、縦境界ライン50bと縦境界ライン50fとの間隔と等間隔だけ離間して、縦境界ライン50bの左側に形成されている。
次に、仮想の境界線50を特定する第2の手法について、図9(b)を参照しながら説明する。
次に、仮想の境界線50を特定する第3の手法について、図9(c)を参照しながら説明する。
次に、仮想の境界線50を特定する第4の手法について、図9(d)を参照しながら説明する。
ここで、ショットキー電極9aの面積は、p型半導体領域4の平面視における面積より大きいことが好ましい。これは、ショットキー電極9aとドリフト領域3aとの間のショットキー障壁はp型半導体領域4とドリフト領域3aとの間のp/n接合の障壁より小さいことから、半導体素子20にサージ電圧が印加された場合に、ショットキー電極9aによってそのサージ電圧が緩和されるので、そのような構成とすると、この効果がより大きくなるからである。
図1及び図2に示すように、半導体層3の上面には、さらにガードリング11が形成されている。ガードリング11は、セル形成領域201と半導体層3の端(チップの端)14との間に、平面視において矩形の環状に2重に形成されている。ここで、ガードリング11は、平面視において矩形の環状に形成されることに限定されず、セル形成領域201の外周を囲んでいればよい。また、ガードリング11は、2重に形成されることに限定されず、1重、3重など、何重に形成されていてもよい。ガードリング11は、ドリフト領域3aと反対の導電型のp型半導体領域で構成されている。
そして、ソース電極6、ゲート電極8、及びショットキー電極9aが形成された半導体層3の表面を覆うように、層間絶縁膜(図示せず)が設けられている。この層間絶縁膜の上面には、ボンディングパッドとして、ソース・ショットキー用パッド12S(図4参照)とゲート用パッド12G(図4参照)とが配設されている。各ボンディングパッド12S,12Gは、Alなどの金属により構成される。ソース・ショットキー用パッド12Sは、ここでは、辺の長さが0.6mm以上の正方形の形状を有している。なお、ソース・ショットキー用パッド12Sの形状は、正方形に限定されない。ソース・ショットキー用パッド12Sは、平面視におけるトランジスタ形成領域10に、縦3×横3の合計9個配設されている。ソース・ショットキー用パッド12Sは、ソース電極6及びショットキー電極9aに電気的に接続されている。また、ゲート用パッド12Gは、平面視におけるトランジスタ形成領域10の外周の端部に1個配設されている。層間絶縁膜には、これを貫通してゲート電極8、ソース電極6、及びショットキー電極9aにそれぞれ接続するように複数の導電体からなるプラグ(図示せず)が設けられている。また、層間絶縁膜の上面には、各プラグとその対応するボンディングパッドとを接続する配線(図示せず)が配設されている。従って、ソース・ショットキー用パッド12Sとソース電極6とはその対応するプラグ及び配線(ソース配線)により接続され、ソース・ショットキー用パッド12Sとショットキー電極9aとはその対応するプラグ及び配線(ショットキー配線)により接続され、ゲート用パッド12Gとゲート電極8とはその対応するプラグ及び配線(ゲート配線)により接続されている。本実施形態の半導体素子20では、ソース・ショットキー用パッド12Sが9個配設されているが、ソース・ショットキー用パッド12Sの個数はこれに限定されない。ソース・ショットキー用パッド12Sの全体には、電界効果トランジスタ90がトランジスタセル100の数だけ並列に接続され、ショットキー電極9aがダイオードセル80の数だけ並列に接続されている。また、本実施形態の半導体素子20では、ゲート用パッド12Gが1個配設されているが、ゲート用パッド12Gの個数はこれに限定されない。すなわち、複数個のゲート用パッド12Gを配設することもできる。この場合においては、上記ソース・ショットキー用パッド12Sの場合と同様に、複数個のゲート用パッド12Gを架橋するようにワイヤ13Gで接続してもよい。
そして、一方向に並ぶ3個のソース・ショットキー用パッド12Sがワイヤ13S(図4参照)によって架橋されるように接続されている。ワイヤ13Sは、AlやAuなどの金属により構成される。ソース・ショットキー用パッド12Sとワイヤ13Sとは、超音波を印加しながらワイヤ13Sをソース・ショットキー用パッド12Sに押し付けることによって接続されている。本実施形態の半導体素子20では、ワイヤ13Sとして0.3mm径のものを用いたが、大電流に耐えられるようにするため、それ以上の径のものを用いることが好ましい。本実施形態の半導体素子20では三本のワイヤ13Sを用いたが、ワイヤ13Sの本数はこれに限定されない。
一方、ゲート用パッド12Gは、ワイヤ13Gにより接続されている。ここで、ワイヤ13Gは、AlやAuなどの金属により構成される。ゲート用パッド12Gとワイヤ13Gとは、超音波を印加しながらワイヤ13Gをゲート用パッド12Gに押し付けることによって接続されている。本実施形態の半導体素子20では、ソース・ショットキー用パッド12Sを接続するワイヤ13Sとして0.3mm径のものを用いたが、ゲート電極8にはそれほど大きな電流を流さないため、ゲート用パッド12Gを接続するワイヤ13Gとしては、より細い径のものを用いることが好ましい。
そして、これらのNiの層を堆積した後、適宜の熱処理が施され、上記電極6,1と半導体との間がオーミックに接続される。
さらに、上記第2の開口内に露出するSiC層3の表面にNiからなる電極が選択的に形成され、この第2の開口内に形成された電極がショットキー電極9aとなる。
その後、ソース電極6、ゲート電極8、及びショットキー電極9aの表面に層間絶縁膜が形成され、この層間絶縁膜に対して、適宜、プラグ、配線、及びボンディングパッド12S、12Gが形成される。
次いで、ボンディングパッド12S、12Gがワイヤ13S、13Gにより適宜接続される。
次に、半導体素子20における電界効果トランジスタ90をトレンチ型で形成した場合と、プレーナ型で形成した場合との比較について説明する。
次に、以上のように構成された半導体素子20の作用効果について説明する。
また、本実施形態の半導体素子20では、ダイオード形成領域9をトランジスタ形成領域10の外周に沿うように配設したため、電界効果トランジスタ90のp型半導体領域4とドリフト領域3aとの間のp/n障壁に比べて小さいエネルギー障壁を有するショットキー接合がトランジスタ形成領域10の外周に沿うように存在することとなり、半導体素子20にサージ電圧が印加された場合に、ショットキー接合部分に優先的にリーク電流が流れ、それにより、サージ電圧が緩和され、半導体素子20の端部(トランジスタ形成領域10の外周部)における破壊が抑制される。
本発明の第2実施形態は、第1実施形態の半導体素子20を用いたアームモジュール(半導体装置)を組み込んだインバータ回路を例示したものである。
図4は本発明の第2実施形態に係る半導体装置としてのアームモジュールの構成を模式的に示す平面図である。図4において図1乃至図3と同一又は相当する部分には同一の符号を付してその説明を省略する。
図5は本発明の第2実施形態に係るインバータ回路の構成を示す回路図である。図5において図8と同一又は相当する部分には同一の符号を付してその説明を省略する。
図6は、本発明の第3実施形態の半導体素子の構成を示す平面図である。図7は、図6の半導体素子の構成の一部を拡大した部分平面図である。図6及び図7において図1及び図2と同一又は相当する部分には同一の符号を付してその説明を省略する。
ショットキー電極9bは、トランジスタ形成領域10の外周に沿って計4個配設されている。なお、ショットキー電極9bの配設される数はこれに限定されない。すなわち、ショットキー電極9bを複数個のセル200に渡って配設したり、ショットキー電極9bの全体又は一部を一体化して形成したりして、その個数が変更されてもかまわない。このような構成としても、上記の第1実施形態と同様の効果を奏する。また、このような構成とすると、構成部品点数が少なくなり、半導体素子20の製造が容易になり、歩留まりが向上する。
上記説明から、当業者にとっては、本発明の多くの改良や他の実施形態が明らかである。従って、上記説明は、例示としてのみ解釈されるべきであり、本発明を実行する最良の態様を当業者に教示する目的で提供されたものである。本発明の精神を逸脱することなく、その構造及び/又は機能の詳細を実質的に変更できる。
止めた。
また、本件発明者らは、半導体素子端部に電界が集中してそこが破壊されることも原因の1つであることを発見した。すなわち、縦型MOSFETでは、オフ状態においてドレイン電極とソース電極との間に電圧を印加すると、その電圧が、ドリフト領域とこれに接するチャネル領域を含むウェルとの間のp/n接合の空乏層に実質的に印加され、その電界はp/n接合において最大になる。一方、特許文献1の構成では、半導体素子が多数のセルを有し、その多数のセルに電界効果トランジスタがそれぞれ形成され、互いに並列接続されている。このような構成では、上記セルが配列された領域中では、p/n接合の電界はほぼ一様であるが、この領域の端において、p/n接合の電界が電界集中により大きくなる。このため、半導体素子の端部に、例えば、メサ構造、ガードリング(フィールドリミッティングリング構造)などを付加している。このような構造を付加すると、当該部分における電界集中が抑制され、その結果、耐圧が向上する。しかし、サージ電圧が印加された場合には、半導体素子の端部における電界が大きくなり、そこが破壊される場合があった。
[0015]
そこで、本発明の半導体素子は、ワイドバンドギャップ半導体からなる半導体層と、該半導体層に該半導体層の上面を含むように形成された第1導電型の第1のソース/ドレイン領域と、前記半導体層に前記上面及び前記第1のソース/ドレイン領域を含むように形成された第2導電型領域と、前記半導体層に前記上面及び前記第2導電型領域を含むように形成された第1導電型のドリフト領域と、少なくとも前記第1のソース/ドレイン領域の前記上面に接するように設けられた第1のソース/ドレイン電極と、ゲート絶縁膜を介して少なくとも前記第2導電型領域の前記上面に対向するように設けられたゲート電極と、前記ドリフト領域にオーミックに接続された第2のソース/ドレイン電極と、を有する複数の電界効果トランジスタと、前記ドリフト領域の前記上面に該上面とショットキー接合を形成するように設けられたショットキー電極と、を備え、前記半導体層は、平面視において仮想の境界線により複数のセルに分割され、前記複数のセルに延在するように前記ドリフト領域及び第2のソース/ドレイン電極が形成され、前記複数のセルは、その中に前記電界効果トランジスタが形成されたトランジスタセルと、その中に前記ショットキー電極が形成されたダイオードセルとで構成され、複
数の前記トランジスタセルがトランジスタ形成領域に互いに隣接して形成され、前記トランジスタ形成領域を囲むように、前記ダイオードセルが1以上形成されたダイオード形成領域が形成されている。
[0016]
このような構成とすると、電界効果トランジスタに存在するp/n障壁に比べて小さいエネルギー障壁を有するショットキー接合が複数の電界効果トランジスタが形成された領域の外周に沿うように存在するので、半導体素子にサージ電圧が印加された場合に、ショットキー接合部分に優先的にリーク電流が流れ、それにより、サージ電圧が緩和され、半導体素子の端部(複数の電界効果トランジスタが形成された領域の外周部)における破壊が抑制される。また、電界効果トランジスタの寄生ダイオードをオンからオフへとスイッチングした場合に、電界効果トランジスタの寄生ダイオードに由来する少数キャリアがショットキー電極により吸収され、高速のスイッチングが行えるようになる。
[0017]
前記第1のソース/ドレイン電極が、前記第1のソース/ドレイン領域及び第2導電型領域の前記上面に接するように設けられていてもよい。
[0018]
前記第1導電型がn型であり、前記第2導電型がp型であってもよい。
[0019]
前記半導体層の上面に、平面視において前記ダイオード形成領域と前記半導体層の端との間に位置するように、ガードリングが形成されていてもよい。
[0020]
前記複数の電界効果トランジスタが形成された領域の外周に沿って、その全周に渡って前記ショットキー電極が配列されていてもよい。
[0021]
前記半導体素子は、前記半導体素子の平面視における面積に対する全ての前記トランジスタセルの平面視における面積の割合が50%以上でかつ99%以下であることが好ましい。
[0022]
前記半導体素子は、前記半導体素子の平面視における面積に対する前記ショットキー電極の面積の割合が1%以上でかつ50%以下であることが好ましい。
[0023]
前記ダイオードセルにおける前記ショットキー電極の面積が前記トランジスタセルにおける前記第2導電型領域の平面視における面積より大きいことが好ましい。
また、本発明は、交流駆動装置のインバータ電源回路を構成する半導体素子として用いることができ、例えば、前記半導体素子がアームモジュールとして組み込まれている
電気機器に適用することができる。
[0024]
このような電気機器によれば、半導体素子の導通損失は電流に電圧を乗じた値(電流×電圧)に対応することから、従来のPN接合ダイオードの順方向電圧に比べてショットキーダイオードの順方向電圧を低く保つことができる。したがって、電気機器のインバータ電源回路においてアームモジュールとして組み込まれている半導体素子の導通損失が、PN接合ダイオードを採用した既存のものに比較して改善する。
[0025]
さらに、電気機器のインバータ電源回路においてアームモジュールとして組み込まれている半導体素子のオン状態からオフ状態への切り替え速度が速くなり、スイッチング損失が低減される。
[0026]
前記交流駆動装置内のインダクタンス負荷によって発生する逆起電力に基づいて、前記電界効果トランジスタの寄生ダイオード及び前記ドリフト領域と該ドリフト領域の上面とショットキー接合を形成するショットキー電極とによって構成されたショットキーダイオードに印加される電圧は、前記ショットキーダイオードの順方向の立ち上がり電圧よりも大きく、かつ前記寄生ダイオードの順方向の立ち上がり電圧より小さくして構成されても良い。
前記交流駆動装置の一例は、前記インバータ電源回路により駆動される交流モータであり、この交流モータにより、例えばエアコンディショナーのコンプレッサが駆動される。
本発明の上記目的、他の目的、特徴、及び利点は、添付図面参照の下、以下の好適な実施態様の詳細な説明から明らかにされる。
発明の効果
[0027]
本発明によれば、高速スイッチング動作とエネルギー損失低減の両立が図れ、かつ電気機器のインダクタンス負荷等による逆起電力に基づく電流集中耐性に優れ、かつ素子端部における破壊が抑制された半導体素子及び電気機器が得られる。
図面の簡単な説明
[0028]
[図1]図1は、本発明の第1実施形態の半導体素子の構成を示す平面図である。
[図2]図2は、図1の半導体素子の構成の一部を拡大した部分平面図である。
[図3]図3は、図1の半導体素子の断面視における構造を示す部分断面図であって、
図1は、本発明の第1実施形態の半導体素子の構成を示す平面図である。図2は、図1の半導体素子の構成の一部を拡大した部分平面図である。図3は、図1の半導体素子の断面視における構造を示す部分断面図であって、図2に示すIII−III線に沿って切断した断面図である。
本発明の第2実施形態は、第1実施形態の半導体素子20を用いたアームモジュール(半導体装置)を組み込んだインバータ回路を例示したものである。
図4は本発明の第2実施形態に係る半導体装置としてのアームモジュールの構成を模式的に示す平面図である。図4において図1乃至図3と同一又は相当する部分には同一の符号を付してその説明を省略する。
図5は本発明の第2実施形態に係るインバータ回路の構成を示す回路図である。図5において図8と同一又は相当する部分には同一の符号を付してその説明を省略する。
図6は、本発明の第3実施形態の半導体素子の構成を示す平面図である。図7は、図6の半導体素子の構成の一部を拡大した部分平面図である。図6及び図7において図1及び図2と同一又は相当する部分には同一の符号を付してその説明を省略する。
2 半導体基板
3 半導体層(SiC層)
3a ドリフト領域
4 p型半導体領域(第2導電型領域)
4a p型半導体領域外周部
4b p型半導体領域中央部
5 ソース領域
6 ソース電極
7 ゲート絶縁膜
8 ゲート電極
9 ダイオード形成領域
9a,9b ショットキー電極
10 トランジスタ形成領域
11 ガードリング(耐圧部材)
12 ボンディングパッド
12S ソース・ショットキー用パッド
12G ゲート用パッド
13S、13G ワイヤ
14 半導体素子端部
15 ドレイン電極端子
16 ソース電極端子
17 ゲート電極端子
18 封止樹脂
20 半導体素子
21 スイッチング素子
22 ダイオード
23 相スイッチング回路
23H 上アーム
23L 下アーム
24 アース電位配線(アース電位)
25 高電位配線(高電位)
26 アームの中点
27 モータ入力端子
28 三相モータ
50 仮想の境界線
50a,50c 横境界ライン
50b,50d,50f 縦境界ライン
50X X部分仮想線
50Y Y部分仮想線
51 ジグザグライン
70 ショットキーダイオード
80 ダイオードセル
90 電界効果トランジスタ(MOSFET)
100 トランジスタセル
200 セル
201 セル形成領域
Claims (12)
- ワイドバンドギャップ半導体からなる半導体層と、該半導体層に該半導体層の上面を含むように形成された第1導電型の第1のソース/ドレイン領域と、前記半導体層に前記上面及び前記第1のソース/ドレイン領域を含むように形成された第2導電型領域と、前記半導体層に前記上面及び前記第2導電型領域を含むように形成された第1導電型のドリフト領域と、少なくとも前記第1のソース/ドレイン領域の前記上面に接するように設けられた第1のソース/ドレイン電極と、ゲート絶縁膜を介して少なくとも前記第2導電型領域の前記上面に対向するように設けられたゲート電極と、前記ドリフト領域にオーミックに接続された第2のソース/ドレイン電極と、を有する複数の電界効果トランジスタと、
前記ドリフト領域の前記上面に該上面とショットキー接合を形成するように設けられたショットキー電極と、を備え、
前記複数の電界効果トランジスタが形成された領域の外周に沿うようにして前記ショットキー電極が設けられている、半導体素子。 - 前記ソース電極が、前記ソース領域及び第2導電型領域の前記上面に接するように設けられている、請求項1に記載の半導体素子。
- 前記第1導電型がn型であり、前記第2導電型がp型である、請求項1に記載の半導体素子。
- 前記半導体層は、平面視において仮想の境界線により複数のセルに分割され、
前記複数のセルに延在するように前記ドリフト領域及びドレイン電極が形成され、
前記複数のセルは、その中に前記電界効果トランジスタが形成されたトランジスタセルと、その中に前記ショットキー電極が形成されたダイオードセルとで構成され、
複数の前記トランジスタセルがトランジスタ形成領域に互いに隣接して形成され、
前記トランジスタ形成領域を囲むように、前記ダイオードセルが1以上形成されたダイオード形成領域が形成されている、請求項1に記載の半導体素子。 - 前記半導体層の上面に、平面視において前記ダイオード形成領域と前記半導体層の端との間に位置するように、ガードリングが形成されている、請求項4に記載の半導体素子。
- 前記複数の電界効果トランジスタが形成された領域の外周に沿って、その全周に渡って前記ショットキー電極が配列されている、請求項1に記載の半導体素子。
- 前記半導体素子の平面視における面積に対する全ての前記トランジスタセルの平面視における面積の割合が50%以上でかつ99%以下である、請求項4に記載の半導体素子。
- 前記半導体素子の平面視における面積に対する前記ショットキー電極の面積の割合が1%以上でかつ50%以下である、請求項1に記載の半導体素子。
- 前記ダイオードセルにおける前記ショットキー電極の面積が前記トランジスタセルにおける前記第2導電型領域の平面視における面積より大きい、請求項4に記載の半導体素子。
- 交流駆動装置と、該交流駆動装置のインバータ電源回路を構成する請求項1乃至9の何れかに記載の半導体素子と、を備え、
前記半導体素子がアームモジュールとして組み込まれている電気機器。 - 前記交流駆動装置内のインダクタンス負荷によって発生する逆起電力に基づいて前記電界効果トランジスタの寄生ダイオードおよび前記ショットキーダイオードに印加される電圧は、前記ショットキーダイオードの順方向の立ち上がり電圧より大きく、かつ前記寄生ダイオードの順方向の立ち上がり電圧より小さくして構成される、請求項10記載の電気機器。
- 前記交流駆動装置は、前記インバータ電源回路により駆動される交流モータである請求項10記載の電気機器。
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JP5720478B2 (ja) | 2011-08-05 | 2015-05-20 | 住友電気工業株式会社 | 炭化珪素半導体装置 |
US8772950B2 (en) * | 2012-11-07 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for flip chip substrate with guard rings outside of a die attach region |
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