JPS648730A - Analog/digital converter - Google Patents

Analog/digital converter

Info

Publication number
JPS648730A
JPS648730A JP16424487A JP16424487A JPS648730A JP S648730 A JPS648730 A JP S648730A JP 16424487 A JP16424487 A JP 16424487A JP 16424487 A JP16424487 A JP 16424487A JP S648730 A JPS648730 A JP S648730A
Authority
JP
Japan
Prior art keywords
signal
register
circuit
conversion
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16424487A
Other languages
Japanese (ja)
Inventor
Toshihiro Noma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16424487A priority Critical patent/JPS648730A/en
Publication of JPS648730A publication Critical patent/JPS648730A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To reduce excess time during the A/D conversion by providing a function capable of switching the resolution of A/D conversion easily in an A/D converter. CONSTITUTION:In giving a control signal 7 to an A/D converter circuit 1 and a register 2, a timing signal outputted from an A/D conversion timing signal output circuit 6 in the circuit 1 is switched. With the control signal 7 at logical 1, signals of T9 and T10 in a shift register 21 are made ineffective and a cycle signal shorter by the timing is fed to the register 2 as an output signal 4. The register 2 receiving the control signal at the same time as the circuit 6 uses a switching circuit to store the signal to 8-bit of low-order LSB and outputs an output signal 5 as a digital signal having the resolution of 8-bit. Through the constitution above, in using the data in the register of 10-bit as the 8-bit data, excess time during the A/D conversion is decreased and instruction steps caused in switching the resolution are saved.
JP16424487A 1987-06-30 1987-06-30 Analog/digital converter Pending JPS648730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16424487A JPS648730A (en) 1987-06-30 1987-06-30 Analog/digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16424487A JPS648730A (en) 1987-06-30 1987-06-30 Analog/digital converter

Publications (1)

Publication Number Publication Date
JPS648730A true JPS648730A (en) 1989-01-12

Family

ID=15789415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16424487A Pending JPS648730A (en) 1987-06-30 1987-06-30 Analog/digital converter

Country Status (1)

Country Link
JP (1) JPS648730A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202120A (en) * 1989-01-30 1990-08-10 Nec Ic Microcomput Syst Ltd Successive approximation type a/d converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202120A (en) * 1989-01-30 1990-08-10 Nec Ic Microcomput Syst Ltd Successive approximation type a/d converter

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