JPS6424514A - D/a converter circuit - Google Patents

D/a converter circuit

Info

Publication number
JPS6424514A
JPS6424514A JP62180675A JP18067587A JPS6424514A JP S6424514 A JPS6424514 A JP S6424514A JP 62180675 A JP62180675 A JP 62180675A JP 18067587 A JP18067587 A JP 18067587A JP S6424514 A JPS6424514 A JP S6424514A
Authority
JP
Japan
Prior art keywords
bit
order
preliminary
inversion
analog conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62180675A
Other languages
Japanese (ja)
Inventor
Kazuhiko Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62180675A priority Critical patent/JPS6424514A/en
Publication of JPS6424514A publication Critical patent/JPS6424514A/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Of Electric Motors In General (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To prevent an analog conversion output within a stationary variation range based upon discontinuity from becoming discontinuously by varying a data value which shifts up or down in digit between its high-order and low-order bit groups and correcting digital data by an increment or decrement generated by the inversion of a preliminary bit. CONSTITUTION:At least one low-order bit of a high-order D/A converter 3 is set as the preliminary bit 5 overlapping with a high-order bit of a low-order D/A converter 4 and when the variation range of the digital data is a range wherein the data is shifted up or down in digit between both bit groups, a data value corresponding to a part where discontinuity is caused owing to the inversion of the preliminary bit 5 is shifted by the preliminary bit. The increment or decrement of the digital data due to the inversion of the preliminary bit 5 is corrected before analog conversion, so the analog conversion output is prevented from becoming discontinuous.
JP62180675A 1987-07-20 1987-07-20 D/a converter circuit Pending JPS6424514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62180675A JPS6424514A (en) 1987-07-20 1987-07-20 D/a converter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62180675A JPS6424514A (en) 1987-07-20 1987-07-20 D/a converter circuit

Publications (1)

Publication Number Publication Date
JPS6424514A true JPS6424514A (en) 1989-01-26

Family

ID=16087343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62180675A Pending JPS6424514A (en) 1987-07-20 1987-07-20 D/a converter circuit

Country Status (1)

Country Link
JP (1) JPS6424514A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05507590A (en) * 1990-07-30 1993-10-28 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Digital-analog conversion system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05507590A (en) * 1990-07-30 1993-10-28 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Digital-analog conversion system

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