JPS57125518A - D-a converter - Google Patents
D-a converterInfo
- Publication number
- JPS57125518A JPS57125518A JP1216381A JP1216381A JPS57125518A JP S57125518 A JPS57125518 A JP S57125518A JP 1216381 A JP1216381 A JP 1216381A JP 1216381 A JP1216381 A JP 1216381A JP S57125518 A JPS57125518 A JP S57125518A
- Authority
- JP
- Japan
- Prior art keywords
- data
- converter
- bit
- bit data
- bits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To obtain a n-bit D/A converter with low cost and good accuracy, by converting n-bit data into analog signals through the use of 2 sets of D/A converters in<n bits. CONSTITUTION:When n-bit data is inputted to a terminal 16, the data in high- order l bit is applied to an operater 13, and 1 at the m-1th bits is reduced from an LSB. The result is applied to a D/A converter 11 and a memory 14, and the l-bit data is converted into an analog signal at the converter 11. In the memory 14, the sum of the data subtracted at the operator 13 and converter output error is stored as the data in n-l+m-1 bits. The l-bit data is inputted from the operator 13, the corresponding data are read out and outputted to an operator 15, where the low-order n-l- bit data and the memory output data are summed, and the error and the subtracted part are outputted after correction. This output n-l+m-bit data is analog-converted at a D/A converter 12. The outputs of the converters 11, 12 are synthesized and picked up from a terminal 19.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1216381A JPS57125518A (en) | 1981-01-29 | 1981-01-29 | D-a converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1216381A JPS57125518A (en) | 1981-01-29 | 1981-01-29 | D-a converter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57125518A true JPS57125518A (en) | 1982-08-04 |
JPS613132B2 JPS613132B2 (en) | 1986-01-30 |
Family
ID=11797769
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1216381A Granted JPS57125518A (en) | 1981-01-29 | 1981-01-29 | D-a converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57125518A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59205863A (en) * | 1983-04-18 | 1984-11-21 | アルカテル・エヌ・ブイ | Programmable encoding/decoding device |
JPS60144024A (en) * | 1984-01-04 | 1985-07-30 | Nec Corp | Error detecting circuit of d/a converter |
JPH0258926A (en) * | 1988-08-24 | 1990-02-28 | Nec Ic Microcomput Syst Ltd | D/a converter |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0534999Y2 (en) * | 1986-12-26 | 1993-09-06 |
-
1981
- 1981-01-29 JP JP1216381A patent/JPS57125518A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59205863A (en) * | 1983-04-18 | 1984-11-21 | アルカテル・エヌ・ブイ | Programmable encoding/decoding device |
JPS60144024A (en) * | 1984-01-04 | 1985-07-30 | Nec Corp | Error detecting circuit of d/a converter |
JPH0258926A (en) * | 1988-08-24 | 1990-02-28 | Nec Ic Microcomput Syst Ltd | D/a converter |
Also Published As
Publication number | Publication date |
---|---|
JPS613132B2 (en) | 1986-01-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS57194625A (en) | Digital to analog converter | |
WO1991005409A3 (en) | Analog-to-digital converter employing a pipelined multi-stage architecture | |
JPS6457824A (en) | Serial/parallel ad converter | |
GB2102227B (en) | Analog to digital converter | |
JPS55100742A (en) | Analog-to-digital converter | |
JPS57125517A (en) | Da conversion circuit | |
DE3277490D1 (en) | Analog to digital converter | |
KR900013725A (en) | Multi-Stage Flash Analog Digital Converter with Voltage Estimator | |
JPS57125518A (en) | D-a converter | |
JP3318219B2 (en) | Digitally compensated multi-bit sigma-delta analog-to-digital converter | |
JPS56164628A (en) | Parallel feedback type analog-to-digital converter | |
DE3685772D1 (en) | DIGITAL / ANALOG CONVERTER. | |
JPS57180230A (en) | Analog-to-digital conversion circuit | |
JPS6243571B2 (en) | ||
JPS5753144A (en) | Digital-analogue converter | |
JPS5799026A (en) | Sequential comparison type a-d converter | |
JPS5799820A (en) | Digital-to-analogue converter | |
JPS5492048A (en) | High resolution digital analogous convertr | |
JPS57124932A (en) | Sequential comparison type a-d converter | |
JPS5930343B2 (en) | Differential nonlinearity correction method for analog-to-digital converters | |
FR2449367A1 (en) | A=D signal converter - has weighted outputs of several low resolution converters summed to provide high resolution output | |
Dighe et al. | New strategies for fast ADC circuits | |
JPS57190418A (en) | Sequential comparison type a-d converter for pcm audio processor | |
JPS57201327A (en) | Digital-to-analog converter | |
JPS57123731A (en) | Correction system of digital-to-analog converter |