JPS6478354A - Switching device for data bus width - Google Patents

Switching device for data bus width

Info

Publication number
JPS6478354A
JPS6478354A JP62235486A JP23548687A JPS6478354A JP S6478354 A JPS6478354 A JP S6478354A JP 62235486 A JP62235486 A JP 62235486A JP 23548687 A JP23548687 A JP 23548687A JP S6478354 A JPS6478354 A JP S6478354A
Authority
JP
Japan
Prior art keywords
bit
data bus
cpu
bus width
order
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62235486A
Other languages
Japanese (ja)
Inventor
Kimio Yamamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Hudson Soft Co Ltd
Original Assignee
Seiko Epson Corp
Hudson Soft Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Hudson Soft Co Ltd filed Critical Seiko Epson Corp
Priority to JP62235486A priority Critical patent/JPS6478354A/en
Priority to GB8818788A priority patent/GB2210239B/en
Priority to KR1019880011052A priority patent/KR960014826B1/en
Publication of JPS6478354A publication Critical patent/JPS6478354A/en
Priority to US07/563,745 priority patent/US5319786A/en
Priority to GB9122388A priority patent/GB2247814B/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/42—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To simplify the interface with a CPU by switching between 8-bit and 16-bit bus widths according to '1' or '0' of a data bus width switching signal outputted to a signal line. CONSTITUTION:The 16-bit data bus width is selected when a CPU 2 generates '0' as a bit width signal. Then the 16-bit data is transferred between a VRAM 7 and a video display controller 1. While the 8-bit data bus width is selected when the CPU 2 generates '1' as the bit width signal. Then the 16-bit data is divided into the low-order and high-order bytes and then transferred. In this case, the low-order or high-order byte of the transferred data is decided based on the contents of a specific bit of an address signal. In such constitution, the interface with the CPU 2 is simplified.
JP62235486A 1987-05-20 1987-09-19 Switching device for data bus width Pending JPS6478354A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP62235486A JPS6478354A (en) 1987-09-19 1987-09-19 Switching device for data bus width
GB8818788A GB2210239B (en) 1987-09-19 1988-08-08 An apparatus for controlling the access of a video memory
KR1019880011052A KR960014826B1 (en) 1987-09-19 1988-08-30 An apparatus for controlling the access of a video memory
US07/563,745 US5319786A (en) 1987-05-20 1990-08-03 Apparatus for controlling a scanning type video display to be divided into plural display regions
GB9122388A GB2247814B (en) 1987-09-19 1991-10-22 An apparatus for controlling the access of a video memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62235486A JPS6478354A (en) 1987-09-19 1987-09-19 Switching device for data bus width

Publications (1)

Publication Number Publication Date
JPS6478354A true JPS6478354A (en) 1989-03-23

Family

ID=16986768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62235486A Pending JPS6478354A (en) 1987-05-20 1987-09-19 Switching device for data bus width

Country Status (1)

Country Link
JP (1) JPS6478354A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03137756A (en) * 1989-10-24 1991-06-12 Matsushita Electric Ind Co Ltd Information processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62192846A (en) * 1986-02-20 1987-08-24 Fujitsu Ltd Bus switching control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62192846A (en) * 1986-02-20 1987-08-24 Fujitsu Ltd Bus switching control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03137756A (en) * 1989-10-24 1991-06-12 Matsushita Electric Ind Co Ltd Information processor

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