JPS55159247A - Address modification system - Google Patents

Address modification system

Info

Publication number
JPS55159247A
JPS55159247A JP6588079A JP6588079A JPS55159247A JP S55159247 A JPS55159247 A JP S55159247A JP 6588079 A JP6588079 A JP 6588079A JP 6588079 A JP6588079 A JP 6588079A JP S55159247 A JPS55159247 A JP S55159247A
Authority
JP
Japan
Prior art keywords
address
register
decimal point
mask circuit
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6588079A
Other languages
Japanese (ja)
Inventor
Takashi Nagashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6588079A priority Critical patent/JPS55159247A/en
Publication of JPS55159247A publication Critical patent/JPS55159247A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable high speed table index, by taking the effetive bit in the address as the displacement in the table and replacing the ineffective bit into the table address.
CONSTITUTION: The mask circuit 4 produces the signal to distinguish the floating decimal point data/fixed decimal point data from the control line 6 and the address stored in the input data stored in the input data register 1 according to the content of the base address register 2 and the master register 3. The address converted with this mask circuit 4 is set to the memory address register 5. Further, the mask circuit 4 selects the number of bits represented in the register 3 as the numeral at LSB side in the memory address from the LSB side of the mantissa in the fixed or floating decimal point number and selects it from the bit corresponding to the register 2 as the numeral at MSB of the address to constitute the memory address.
COPYRIGHT: (C)1980,JPO&Japio
JP6588079A 1979-05-28 1979-05-28 Address modification system Pending JPS55159247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6588079A JPS55159247A (en) 1979-05-28 1979-05-28 Address modification system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6588079A JPS55159247A (en) 1979-05-28 1979-05-28 Address modification system

Publications (1)

Publication Number Publication Date
JPS55159247A true JPS55159247A (en) 1980-12-11

Family

ID=13299724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6588079A Pending JPS55159247A (en) 1979-05-28 1979-05-28 Address modification system

Country Status (1)

Country Link
JP (1) JPS55159247A (en)

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