JPS5549749A - Microprogram control data processing system - Google Patents

Microprogram control data processing system

Info

Publication number
JPS5549749A
JPS5549749A JP12336878A JP12336878A JPS5549749A JP S5549749 A JPS5549749 A JP S5549749A JP 12336878 A JP12336878 A JP 12336878A JP 12336878 A JP12336878 A JP 12336878A JP S5549749 A JPS5549749 A JP S5549749A
Authority
JP
Japan
Prior art keywords
address register
data
byte
increased
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12336878A
Other languages
Japanese (ja)
Inventor
Nobuyuki Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12336878A priority Critical patent/JPS5549749A/en
Publication of JPS5549749A publication Critical patent/JPS5549749A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make data read high-speed by providing a buffer register having a width larger than the bus width in the data bus line.
CONSTITUTION: Data read from main storage device 1 and the buffer register on the data bus line are defined as two-byte width and three-byte width, respectively. It is found that the start of read data is on the word boundary of one-word two bytes if contents of address register 2 are even and the start above is in the middle of boundaries if odd. When contents of address register 2 are even and read data has a three-byte length, two bytes are set by the first access, and address register 2 is increased by 2, and next, one byte is set, and address register 2 is increased by 1. When contents of address register 2 are odd, one-byte components of data are set, and address register 2 is increased by 1, and after that, two-byte components of data are set continuously, and address register 2 is increased by 2.
COPYRIGHT: (C)1980,JPO&Japio
JP12336878A 1978-10-06 1978-10-06 Microprogram control data processing system Pending JPS5549749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12336878A JPS5549749A (en) 1978-10-06 1978-10-06 Microprogram control data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12336878A JPS5549749A (en) 1978-10-06 1978-10-06 Microprogram control data processing system

Publications (1)

Publication Number Publication Date
JPS5549749A true JPS5549749A (en) 1980-04-10

Family

ID=14858843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12336878A Pending JPS5549749A (en) 1978-10-06 1978-10-06 Microprogram control data processing system

Country Status (1)

Country Link
JP (1) JPS5549749A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60114895A (en) * 1983-11-25 1985-06-21 富士通機電株式会社 Fluid sign display unit
JPS63196967A (en) * 1987-02-10 1988-08-15 Fujitsu Ltd Data transfer control equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60114895A (en) * 1983-11-25 1985-06-21 富士通機電株式会社 Fluid sign display unit
JPS63196967A (en) * 1987-02-10 1988-08-15 Fujitsu Ltd Data transfer control equipment

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