JPS6458016A - Digital delay circuit - Google Patents
Digital delay circuitInfo
- Publication number
- JPS6458016A JPS6458016A JP62216237A JP21623787A JPS6458016A JP S6458016 A JPS6458016 A JP S6458016A JP 62216237 A JP62216237 A JP 62216237A JP 21623787 A JP21623787 A JP 21623787A JP S6458016 A JPS6458016 A JP S6458016A
- Authority
- JP
- Japan
- Prior art keywords
- data
- ram
- address
- supplied
- serial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pulse Circuits (AREA)
Abstract
PURPOSE:To produce a delay circuit with no use of a multi-stage shift register by using a serial/parallel converting circuit, a RAM and a +1 adder to form a one-cycle delay circuit. CONSTITUTION:The serial data supplied as the serial bit signals are arranged by a serial/parallel converting circuit 11 in a prescribed unit and then supplied to a RAM 12 as the data groups every 8 bits, for example, via a data bus. At the same time, a signal pointing a data writing address via a switch gate 15 is supplied to the RAM 12 from an address counter 13 via an address bus. The input data is also stored temporarily into the RAM 12. When the data is read out, a command signal is supplied to the RAM 12 from the counter 13 to point a reading address. Then +1 is given to the reading address command signal from a +1 adder 14 connected to the next stage of the counter 13. Thus the output data of the RAM 12 receives +1 from the writing address and is turned into the data preceding by a cycle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62216237A JPS6458016A (en) | 1987-08-28 | 1987-08-28 | Digital delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62216237A JPS6458016A (en) | 1987-08-28 | 1987-08-28 | Digital delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6458016A true JPS6458016A (en) | 1989-03-06 |
Family
ID=16685423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62216237A Pending JPS6458016A (en) | 1987-08-28 | 1987-08-28 | Digital delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6458016A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014504425A (en) * | 2010-11-05 | 2014-02-20 | クラトス・アナリテイカル・リミテツド | Timing device and method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6157115A (en) * | 1984-08-29 | 1986-03-24 | Fujitsu Ltd | Data delay circuit |
| JPS6251387A (en) * | 1985-08-30 | 1987-03-06 | Hitachi Ltd | Picture memory |
-
1987
- 1987-08-28 JP JP62216237A patent/JPS6458016A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6157115A (en) * | 1984-08-29 | 1986-03-24 | Fujitsu Ltd | Data delay circuit |
| JPS6251387A (en) * | 1985-08-30 | 1987-03-06 | Hitachi Ltd | Picture memory |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014504425A (en) * | 2010-11-05 | 2014-02-20 | クラトス・アナリテイカル・リミテツド | Timing device and method |
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