JPS55161409A - Input delay circuit - Google Patents

Input delay circuit

Info

Publication number
JPS55161409A
JPS55161409A JP6976179A JP6976179A JPS55161409A JP S55161409 A JPS55161409 A JP S55161409A JP 6976179 A JP6976179 A JP 6976179A JP 6976179 A JP6976179 A JP 6976179A JP S55161409 A JPS55161409 A JP S55161409A
Authority
JP
Japan
Prior art keywords
memory
delay circuit
control
input delay
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6976179A
Other languages
Japanese (ja)
Inventor
Toshikazu Ida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chino Works Ltd
Original Assignee
Chino Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chino Works Ltd filed Critical Chino Works Ltd
Priority to JP6976179A priority Critical patent/JPS55161409A/en
Publication of JPS55161409A publication Critical patent/JPS55161409A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/04—Shift registers

Landscapes

  • Recording Measured Values (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE:To make the constitution of an input delay circuit simple and cheap, by providing a memory circuit and delaying read times of n-number memory addresses for one another by time T. CONSTITUTION:Analogue signal inputs 18a-18n are stored successively in respective memory segments of memory unit 8 through A/D converter 7 by clock pulses from control circuit 17. In respective memory segments, memory addresses are shifted successively; and when the control reaches the last address, the control is returned to the first address. Memory contents are read from respective memory segments with a delay of time T. They are supplied to recording pens 1b-1n through D/A converter 9 and analogue switches 5a-5n and 6a-6n.
JP6976179A 1979-06-04 1979-06-04 Input delay circuit Pending JPS55161409A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6976179A JPS55161409A (en) 1979-06-04 1979-06-04 Input delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6976179A JPS55161409A (en) 1979-06-04 1979-06-04 Input delay circuit

Publications (1)

Publication Number Publication Date
JPS55161409A true JPS55161409A (en) 1980-12-16

Family

ID=13412098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6976179A Pending JPS55161409A (en) 1979-06-04 1979-06-04 Input delay circuit

Country Status (1)

Country Link
JP (1) JPS55161409A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52113241A (en) * 1976-03-19 1977-09-22 Matsushita Electric Ind Co Ltd Recorder

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52113241A (en) * 1976-03-19 1977-09-22 Matsushita Electric Ind Co Ltd Recorder

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