JPS5469044A - Input/output control system for lsi - Google Patents

Input/output control system for lsi

Info

Publication number
JPS5469044A
JPS5469044A JP13546377A JP13546377A JPS5469044A JP S5469044 A JPS5469044 A JP S5469044A JP 13546377 A JP13546377 A JP 13546377A JP 13546377 A JP13546377 A JP 13546377A JP S5469044 A JPS5469044 A JP S5469044A
Authority
JP
Japan
Prior art keywords
input
bus
output
lsi1
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13546377A
Other languages
Japanese (ja)
Inventor
Tomohiro Shimizu
Yutaka Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP13546377A priority Critical patent/JPS5469044A/en
Publication of JPS5469044A publication Critical patent/JPS5469044A/en
Pending legal-status Critical Current

Links

Landscapes

  • Calculators And Similar Devices (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To decrease the number of the input/output terminal of LSI and thus to enhance the economical property by using the terminal to which the key input data is supplied as the input terminal and carrying out input and output for the data and the external memory control signal via the input terminal.
CONSTITUTION: The ON/OFF information of the key detected every line is delivered from key input pert 2 in the form of the 4-bit data and then supplied to LSI1 formed into one chip via data bus D3 to undergo the fixed process. Terminals KI1WKI4 of LSI11 connected with D3 are used in common as part of the address designation output terimnal to external memory RAM41W44. In other words, LSI1 is connected to input part 2 via bus D3. At the same time, part 2 is connected to terminals 00Wo3 of RAM41W44 via four pieces of address bus A1, and the address designation output at LSI1 is delivered for lower-rank four bits to KI1W KI4 to be supplied to prt 2 via D3 and then to RAM41W44 via bus A1.
COPYRIGHT: (C)1979,JPO&Japio
JP13546377A 1977-11-11 1977-11-11 Input/output control system for lsi Pending JPS5469044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13546377A JPS5469044A (en) 1977-11-11 1977-11-11 Input/output control system for lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13546377A JPS5469044A (en) 1977-11-11 1977-11-11 Input/output control system for lsi

Publications (1)

Publication Number Publication Date
JPS5469044A true JPS5469044A (en) 1979-06-02

Family

ID=15152291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13546377A Pending JPS5469044A (en) 1977-11-11 1977-11-11 Input/output control system for lsi

Country Status (1)

Country Link
JP (1) JPS5469044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61286970A (en) * 1985-06-14 1986-12-17 Toshiba Corp Documentation device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61286970A (en) * 1985-06-14 1986-12-17 Toshiba Corp Documentation device

Similar Documents

Publication Publication Date Title
EP0294632A3 (en) Logical synthesis
EP0118978A3 (en) Address sequencer for pattern processing system
JPS648717A (en) Pseudo noise series code generating circuit
JPS5469044A (en) Input/output control system for lsi
JPS5685130A (en) Rom access circuit
JPS5696350A (en) Memory extension system
JPS5622292A (en) Memory element
JPS5542308A (en) Semiconductor memory unit
JPS55157048A (en) Address output circuit
JPS54161854A (en) Input/output control system for information processor
JPS5488038A (en) Data processor
JPS55109056A (en) Data process system
JPS54137251A (en) Code conversion system
JPS55121543A (en) Area decision circuit
JPS5650423A (en) Initial value set system in information processor
JPS5674666A (en) Voltage level generator
JPS5384437A (en) Control system for test pattern generation
JPS5474642A (en) Operation circuit
JPS6458016A (en) Digital delay circuit
JPS54150935A (en) Memory switching device
JPS5599660A (en) Trigger method for digital logic signal analyzer
JPS5661096A (en) Error detection system for read only memory electrically erasable
JPS55122285A (en) Substitute control system in buffer memory
JPS6443891A (en) Semiconductor memory device
JPS55134460A (en) Address conversion unit