JPS645097A - Ceramic multilayer interconnection substrate - Google Patents

Ceramic multilayer interconnection substrate

Info

Publication number
JPS645097A
JPS645097A JP16167987A JP16167987A JPS645097A JP S645097 A JPS645097 A JP S645097A JP 16167987 A JP16167987 A JP 16167987A JP 16167987 A JP16167987 A JP 16167987A JP S645097 A JPS645097 A JP S645097A
Authority
JP
Japan
Prior art keywords
hole
layer
ceramic multilayer
filling
multilayer interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16167987A
Other languages
Japanese (ja)
Inventor
Yoshiya Kudou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16167987A priority Critical patent/JPS645097A/en
Publication of JPS645097A publication Critical patent/JPS645097A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To eliminate generation of cracks to obtain a ceramic multilayer interconnection substrate with high density by filling the central part of a through hole with an insulating material. CONSTITUTION:A conductive layer 3 for through hole is formed on the inwall of a through hole 2 of a substrate insulating layer 1. A filling layer 6 of the same component as that of the insulating layer 1 is formed in the through hole 2. And a printed conductive layer 4 is formed on each of both surfaces of the substrate body comprising the insulating layer 1 and the filling layer 6. Then, the ratio which the conductive layer 3 forms is so small that the stress, which results from the difference of the thermal expansion coefficient between the insulating layer 1 and the filling members 3, 6 in the through hole 1 and stresses between upper and lower surfaces of the through hole 2, is reduced. As a result, cracks are prevented from being generating in the portion A. Therefore, a ceramic multilayer interconnection substrate with high density can be obtained.
JP16167987A 1987-06-29 1987-06-29 Ceramic multilayer interconnection substrate Pending JPS645097A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16167987A JPS645097A (en) 1987-06-29 1987-06-29 Ceramic multilayer interconnection substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16167987A JPS645097A (en) 1987-06-29 1987-06-29 Ceramic multilayer interconnection substrate

Publications (1)

Publication Number Publication Date
JPS645097A true JPS645097A (en) 1989-01-10

Family

ID=15739782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16167987A Pending JPS645097A (en) 1987-06-29 1987-06-29 Ceramic multilayer interconnection substrate

Country Status (1)

Country Link
JP (1) JPS645097A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5093186A (en) * 1989-09-26 1992-03-03 Ngk Spark Plug Co., Ltd. Multilayer ceramic wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5093186A (en) * 1989-09-26 1992-03-03 Ngk Spark Plug Co., Ltd. Multilayer ceramic wiring board

Similar Documents

Publication Publication Date Title
EP0344720A3 (en) Method of producing electrical connection members
EP0362161A3 (en) Method of manufacturing a substrate for microwave integrated circuits
JPS645097A (en) Ceramic multilayer interconnection substrate
JPS5797634A (en) Hybrid integrated circuit
DE3377454D1 (en) Method and apparatus for the selective and self-adjusting deposition of metal layers and application of this method
JPS6441244A (en) Manufacture of semiconductor device
TW370705B (en) Method to produce a silicon-capacitor
JPS5522863A (en) Manufacturing method for semiconductor device
EP0347792A3 (en) Multi-layer wirings on a semiconductor device and fabrication method
JPS646385A (en) Electrical connection structure of circuit substrates
JPS645098A (en) Ceramic multilayer interconnection substrate
JPS6457653A (en) Mounting structure of hybrid integrated circuit component
JPS6448437A (en) Electrode structure
JPS6439042A (en) Semiconductor integrated circuit
JPS6414914A (en) Jig for manufacture of semiconductor
JPS6411379A (en) Superconducting film structure
JPS6432655A (en) Substrate for loading semiconductor element
JPS6432662A (en) Structure of semiconductor package
JPS6430228A (en) Manufacture of semiconductor device
JPS6478412A (en) Formation of through hole in thin film multilayer body
JPS558057A (en) Semiconductor
JPS647696A (en) High density package hybrid integrated circuit
JPS5591835A (en) Electronic device
JPS6433950A (en) Structure for mounting semiconductor element
JPS57201050A (en) Multilayer wiring structure