JPS558057A - Semiconductor - Google Patents

Semiconductor

Info

Publication number
JPS558057A
JPS558057A JP8050678A JP8050678A JPS558057A JP S558057 A JPS558057 A JP S558057A JP 8050678 A JP8050678 A JP 8050678A JP 8050678 A JP8050678 A JP 8050678A JP S558057 A JPS558057 A JP S558057A
Authority
JP
Japan
Prior art keywords
layer
metallized layers
ceramic
wirings
cap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8050678A
Other languages
Japanese (ja)
Inventor
Toyoji Tsunoda
Masao Mitani
Akizo Toda
Takeshi Fujita
Masanori Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8050678A priority Critical patent/JPS558057A/en
Publication of JPS558057A publication Critical patent/JPS558057A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: For facilitating connection, to provide a conductor layer and a sealing metallized layer on the inner surface of a ceramic cap before covering a ceramic substrate having single or multi-layer wiring with said ceramic cap.
CONSTITUTION: Inner wirings 2 and 3, through hole wirings 4, surface layer wirings 6 and power supply wiring conductors 16 are provided on a ceramic substrate 1 in usual manner, and sealing metallized layers 13 are formed at the ends thereof. Next, said metallized layers are covered with a ceramic cap 100 which are made of the green mixture sheet of alumina and organic binder, and power supply conductor layer 90 and metallized layers 110 of the fine particles of W placed on the inner side of said sheet by printing method, with a clearance provided under said conductor layer 90. Construction is made as described heretofore, IC chip 8 is fastened on said substrate 1, a given mode of wiring is completed, said cap 100 is placed, said conductors 90 and 16 are contacted, and said metallized layers 110 and 13 are soldered 13.
COPYRIGHT: (C)1980,JPO&Japio
JP8050678A 1978-07-04 1978-07-04 Semiconductor Pending JPS558057A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8050678A JPS558057A (en) 1978-07-04 1978-07-04 Semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8050678A JPS558057A (en) 1978-07-04 1978-07-04 Semiconductor

Publications (1)

Publication Number Publication Date
JPS558057A true JPS558057A (en) 1980-01-21

Family

ID=13720190

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8050678A Pending JPS558057A (en) 1978-07-04 1978-07-04 Semiconductor

Country Status (1)

Country Link
JP (1) JPS558057A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6014456A (en) * 1983-07-06 1985-01-25 Hitachi Ltd Semiconductor device
JPS6041331A (en) * 1984-07-10 1985-03-05 Matsushita Electric Ind Co Ltd Radio receiver
JPS6180847A (en) * 1984-09-27 1986-04-24 Clarion Co Ltd Highly integrated functional module
JPH05501332A (en) * 1989-09-27 1993-03-11 ジーイーシー―マーコニ・エレクトロニック・システムス・コーポレーション Electronic implementation of hybrid module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6014456A (en) * 1983-07-06 1985-01-25 Hitachi Ltd Semiconductor device
JPS6041331A (en) * 1984-07-10 1985-03-05 Matsushita Electric Ind Co Ltd Radio receiver
JPS6180847A (en) * 1984-09-27 1986-04-24 Clarion Co Ltd Highly integrated functional module
JPH05501332A (en) * 1989-09-27 1993-03-11 ジーイーシー―マーコニ・エレクトロニック・システムス・コーポレーション Electronic implementation of hybrid module

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