JPS6436218A - Frequency division circuit - Google Patents
Frequency division circuitInfo
- Publication number
- JPS6436218A JPS6436218A JP19166287A JP19166287A JPS6436218A JP S6436218 A JPS6436218 A JP S6436218A JP 19166287 A JP19166287 A JP 19166287A JP 19166287 A JP19166287 A JP 19166287A JP S6436218 A JPS6436218 A JP S6436218A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- type
- output
- goes
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/02—Input circuits
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To make the duty nearly 50% by providing an n-stage of D type FF, a logic circuit, and a D type FF circuit using an output of the logic circuit as the clock input, using the inverted output as the data input and using the output signal for plural D type FF input data. CONSTITUTION:The output signal S10 of the D type FF5 goes to H at time t1 when the clock signal S2 rises at first from a time t0 when a reset signal S1 goes to H. Since the D type FF3 uses the clock signal inverted by the inverter 7 to latch the signal S10 at a time t2, the signal S6 goes to H. The said D type FF5 inverts the output synchronously with the time t3 when the clock signal S2 descends next and the output signal S10 goes to L. Since the D type FF3 latches the signal S10 at a time t4, the signal S6 goes to L. In checking the output signal S10 of the D type FF5, the duty is brought into 50%.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19166287A JPS6436218A (en) | 1987-07-31 | 1987-07-31 | Frequency division circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19166287A JPS6436218A (en) | 1987-07-31 | 1987-07-31 | Frequency division circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6436218A true JPS6436218A (en) | 1989-02-07 |
Family
ID=16278371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19166287A Pending JPS6436218A (en) | 1987-07-31 | 1987-07-31 | Frequency division circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6436218A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140211895A1 (en) * | 2011-08-05 | 2014-07-31 | St-Ericsson Sa | Frequency Division |
JP2016036151A (en) * | 2008-09-19 | 2016-03-17 | クゥアルコム・インコーポレイテッドQualcomm Incorporated | Latch structure, frequency divider, and methods for operating the same |
-
1987
- 1987-07-31 JP JP19166287A patent/JPS6436218A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016036151A (en) * | 2008-09-19 | 2016-03-17 | クゥアルコム・インコーポレイテッドQualcomm Incorporated | Latch structure, frequency divider, and methods for operating the same |
US20140211895A1 (en) * | 2011-08-05 | 2014-07-31 | St-Ericsson Sa | Frequency Division |
US9485079B2 (en) * | 2011-08-05 | 2016-11-01 | St-Ericsson Sa | Frequency division |
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