JPS55112042A - 1/3-divider circuit - Google Patents

1/3-divider circuit

Info

Publication number
JPS55112042A
JPS55112042A JP1935479A JP1935479A JPS55112042A JP S55112042 A JPS55112042 A JP S55112042A JP 1935479 A JP1935479 A JP 1935479A JP 1935479 A JP1935479 A JP 1935479A JP S55112042 A JPS55112042 A JP S55112042A
Authority
JP
Japan
Prior art keywords
inverter
interval
output
level
features
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1935479A
Other languages
Japanese (ja)
Other versions
JPS6238891B2 (en
Inventor
Norihiko Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1935479A priority Critical patent/JPS55112042A/en
Publication of JPS55112042A publication Critical patent/JPS55112042A/en
Publication of JPS6238891B2 publication Critical patent/JPS6238891B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/3568—Multistable circuits

Landscapes

  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a divider circuit which features a small number of elements, a small amount of power consumption and a high-speed operation each, by using the inverter in which p (or n) channel type MISFET plus a pair of n (or P) channel type MISFET which are connected in series. CONSTITUTION:Input clock pulse phi features the L level with time interval t1, and thus the output of inverter 54 features the H level. With interval t2 pulse phi is shifted by inverter 50 at the rise of the pulse, and the output changes to the L level. And with interval t3 the shift is given by inverter 51, and the output changes to the H level. The signal varies the output of inverters 52, 53 and 54 with intervals t4, t5 and t6 each. And the output of inverter 54 varies inverters 51 and 52 at interval t6. Then the signal of inverter 52 is transmitted again to inverter 53 at the rise of inverter 54 and with interval t1, thus carrying out the 1/3-division.
JP1935479A 1979-02-21 1979-02-21 1/3-divider circuit Granted JPS55112042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1935479A JPS55112042A (en) 1979-02-21 1979-02-21 1/3-divider circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1935479A JPS55112042A (en) 1979-02-21 1979-02-21 1/3-divider circuit

Publications (2)

Publication Number Publication Date
JPS55112042A true JPS55112042A (en) 1980-08-29
JPS6238891B2 JPS6238891B2 (en) 1987-08-20

Family

ID=11997036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1935479A Granted JPS55112042A (en) 1979-02-21 1979-02-21 1/3-divider circuit

Country Status (1)

Country Link
JP (1) JPS55112042A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102291120A (en) * 2011-06-17 2011-12-21 宁波大学 Ternary heat insulation D trigger and four-bit ternary heat insulation synchronous reversible counter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102291120A (en) * 2011-06-17 2011-12-21 宁波大学 Ternary heat insulation D trigger and four-bit ternary heat insulation synchronous reversible counter
CN102291120B (en) * 2011-06-17 2013-12-04 宁波大学 Ternary heat insulation D trigger and four-bit ternary heat insulation synchronous reversible counter

Also Published As

Publication number Publication date
JPS6238891B2 (en) 1987-08-20

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