JPS6461116A - Delay circuit - Google Patents
Delay circuitInfo
- Publication number
- JPS6461116A JPS6461116A JP62218203A JP21820387A JPS6461116A JP S6461116 A JPS6461116 A JP S6461116A JP 62218203 A JP62218203 A JP 62218203A JP 21820387 A JP21820387 A JP 21820387A JP S6461116 A JPS6461116 A JP S6461116A
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- output
- driven
- frequency division
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Networks Using Active Elements (AREA)
- Pulse Circuits (AREA)
Abstract
PURPOSE:To increase the retarded bit number with flip-flops of fewer number than that employed in a conventional circuit by driving a D flip-flop by a frequency division output. CONSTITUTION:A clock signal 3 is frequency-divided by a T flip-flop T1 and its output is frequency-divided by a T flip-flop T2. A D flip-flop D1 is driven by a 1/4 frequency division waveform and latches a data signal 1 and gives an output. A D flip-flop D2 is driven by a 1/2 frequency division waveform and latches the output of the D2 to give an output. Moreover, a D flip-flop D3 is driven by the clock signal 3 to latch the flip-flop D2 to given an output. In detecting the leading and trailing of the data signal 1, since a reset circuit 5 resets the T flip-flops T1, T2, a signal being a result of retarding the data signal 1 by a prescribed time is obtained as an output 2 at all times.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62218203A JP2594571B2 (en) | 1987-08-31 | 1987-08-31 | Delay circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62218203A JP2594571B2 (en) | 1987-08-31 | 1987-08-31 | Delay circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6461116A true JPS6461116A (en) | 1989-03-08 |
JP2594571B2 JP2594571B2 (en) | 1997-03-26 |
Family
ID=16716237
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62218203A Expired - Lifetime JP2594571B2 (en) | 1987-08-31 | 1987-08-31 | Delay circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2594571B2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5325346A (en) * | 1976-08-20 | 1978-03-09 | Matsushita Electric Ind Co Ltd | Digital delay circuit |
JPS55676A (en) * | 1979-01-26 | 1980-01-07 | Hitachi Ltd | Pulse delay circuit |
JPS58165419A (en) * | 1982-03-26 | 1983-09-30 | Toshiba Corp | Phase shifter |
-
1987
- 1987-08-31 JP JP62218203A patent/JP2594571B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5325346A (en) * | 1976-08-20 | 1978-03-09 | Matsushita Electric Ind Co Ltd | Digital delay circuit |
JPS55676A (en) * | 1979-01-26 | 1980-01-07 | Hitachi Ltd | Pulse delay circuit |
JPS58165419A (en) * | 1982-03-26 | 1983-09-30 | Toshiba Corp | Phase shifter |
Also Published As
Publication number | Publication date |
---|---|
JP2594571B2 (en) | 1997-03-26 |
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