JPS5566141A - Programmable counter - Google Patents
Programmable counterInfo
- Publication number
- JPS5566141A JPS5566141A JP13953178A JP13953178A JPS5566141A JP S5566141 A JPS5566141 A JP S5566141A JP 13953178 A JP13953178 A JP 13953178A JP 13953178 A JP13953178 A JP 13953178A JP S5566141 A JPS5566141 A JP S5566141A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- counter
- register
- supplied
- bit shift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/665—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To prevent the lowering of the maximum active frequency by using the 1-bit shift register to the flip-flop at the first step of the counter to read in the preset of the flip-flop of the first step is the form of the serial signal. CONSTITUTION:Down-counter 1 which is driven by input clock pulse 10 is provided along with detector circuit 2 which detects whether the contents of counter 1 is ''4'' or not. The output of circuit 2 is applied to 1-bit shift registers 3-5 which supply pulse 10, and preset enable signal 11 of register 5 is supplied to counter 1. At the same time, pulse 10 is supplied to the input side of circuit 1 as well as to 1-bit shift registers 6 and 7 of the first step. Furthermore, logic values P1-Pn obtained by coding the division ratio are supplied to FFF2-Fn of circuit 1. Then signal 11 is read into register 7 forming the FF of the first step of counter 1 via NAND circuit NA1, register 6 and NOR circuit NR1 each and in the form of the serial signal. Thus the lowering can be prevented for the maximum active frequency.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13953178A JPS5566141A (en) | 1978-11-13 | 1978-11-13 | Programmable counter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13953178A JPS5566141A (en) | 1978-11-13 | 1978-11-13 | Programmable counter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5566141A true JPS5566141A (en) | 1980-05-19 |
Family
ID=15247440
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13953178A Pending JPS5566141A (en) | 1978-11-13 | 1978-11-13 | Programmable counter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5566141A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04117727A (en) * | 1990-09-06 | 1992-04-17 | Mitsubishi Electric Corp | Counter circuit |
-
1978
- 1978-11-13 JP JP13953178A patent/JPS5566141A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04117727A (en) * | 1990-09-06 | 1992-04-17 | Mitsubishi Electric Corp | Counter circuit |
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