JPS641649Y2 - - Google Patents
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- Publication number
- JPS641649Y2 JPS641649Y2 JP1563384U JP1563384U JPS641649Y2 JP S641649 Y2 JPS641649 Y2 JP S641649Y2 JP 1563384 U JP1563384 U JP 1563384U JP 1563384 U JP1563384 U JP 1563384U JP S641649 Y2 JPS641649 Y2 JP S641649Y2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- current
- under test
- amplifier
- device under
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012360 testing method Methods 0.000 claims description 25
- 238000005259 measurement Methods 0.000 description 18
- 239000004065 semiconductor Substances 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 7
- 238000001514 detection method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Description
【考案の詳細な説明】
〈考案の技術分野〉
この考案は例えば半導体素子又は半導体集積回
路の端子間の直流的な電圧電流特性を測定し半導
体素子或は半導体集積回路の良否を判定する装置
或は部品が実装されたプリント配線基板の外部端
子間の直流的な電圧電流特性を測定し回路が予定
通り組立てられているか否かを判定する装置等に
利用することができる電圧印加電流測定装置に関
する。[Detailed Description of the Invention] <Technical Field of the Invention> This invention is an apparatus or device for determining the quality of a semiconductor element or a semiconductor integrated circuit by measuring DC voltage-current characteristics between the terminals of a semiconductor element or a semiconductor integrated circuit, for example. relates to a voltage applied current measuring device that can be used as a device for measuring direct current voltage and current characteristics between external terminals of a printed wiring board on which components are mounted and determining whether a circuit is assembled as planned. .
〈従来技術〉
第１図に従来の電圧印加電流測定装置を示す。
図中１は定電圧源を示す。この定電圧源１は例え
ば制御器２と制御器２から出力されるデイジタル
信号を電圧信号に変換するDA変換器３と、この
DA変換器３から出力される電圧信号を増幅し、
ケーブル５及び６を通じて測定端子７及び８に一
定電圧を与える増幅器４と、測定端子７及び８に
与えられる電圧をケーブル９及び１０を介して高
インピーダンスで取出して増幅器４の反転入力端
子に帰還するボルテージフオロワ１１とにより構
成される。<Prior Art> Fig. 1 shows a conventional voltage applied current measuring device.
In the figure, 1 indicates a constant voltage source. This constant voltage source 1 includes, for example, a controller 2, a DA converter 3 that converts a digital signal output from the controller 2 into a voltage signal, and a DA converter 3 that converts a digital signal output from the controller 2 into a voltage signal.
Amplify the voltage signal output from the DA converter 3,
An amplifier 4 applies a constant voltage to measurement terminals 7 and 8 through cables 5 and 6, and the voltage applied to measurement terminals 7 and 8 is taken out at high impedance through cables 9 and 10 and fed back to the inverting input terminal of amplifier 4. It is composed of a voltage follower 11.
測定端子７と８の間には被測定素子１２を接続
する。この被測定素子１２は単体の半導体素子或
は半導体集積回路の端子ピン相互間の回路部分或
は部品が実装された状態のプリント配線基板の外
部端子相互間のようなものとする。これらの被測
定素子をこゝでは等価的に抵抗器Ｒとコンデンサ
Ｃの並列接続回路として示す。 A device to be measured 12 is connected between measurement terminals 7 and 8 . The device to be measured 12 is assumed to be a single semiconductor device, a circuit portion between terminal pins of a semiconductor integrated circuit, or a portion between external terminals of a printed wiring board on which components are mounted. These elements to be measured are equivalently shown here as a parallel connection circuit of a resistor R and a capacitor C.
定電圧源１の動作としては測定端子７及び８に
印加する電圧をボルテージフオロワ１１により増
幅器４の入力点に帰還し、この帰還動作により
DA変換器３から増幅器４に与えた電圧が測定端
子７及び８に正確に印加されるように動作する。
ボルテージフオロワ１１はケーブル９及び１０の
直流抵抗による影響を除去する目的で使用するも
のである。つまり測定端子７及び８に電圧を印加
するケーブル５及び６は電圧印加用ケーブルであ
る。増幅器４から被測定素子１２に供給する電流
I0はケーブル５及び６を通じて正と負の電源１３
と１４の共通電位点１５に流れ込む。ケーブル９
及び１０は電圧検出用ケーブルである。ケーブル
１０は定電圧源１を構成する回路の共通電位点１
６に接続される。 The constant voltage source 1 operates by feeding back the voltage applied to the measurement terminals 7 and 8 to the input point of the amplifier 4 by the voltage follower 11.
It operates so that the voltage applied from the DA converter 3 to the amplifier 4 is accurately applied to the measurement terminals 7 and 8.
The voltage follower 11 is used for the purpose of eliminating the influence of DC resistance of the cables 9 and 10. In other words, the cables 5 and 6 that apply voltage to the measurement terminals 7 and 8 are voltage application cables. Current supplied from amplifier 4 to device under test 12
I 0 connects the positive and negative power supplies 13 through cables 5 and 6
and 14 into a common potential point 15. cable 9
and 10 are voltage detection cables. The cable 10 is a common potential point 1 of the circuit that constitutes the constant voltage source 1
Connected to 6.
一方、１７は電流制限回路を示す。この電流制
限回路１７は被測定素子１２に許容量以上の電流
が流れ込んで素子を破損させることを防止する目
的で設けられる。その構造は増幅器４の出力側に
電流検出用抵抗器１８を直列接続し、この電流検
出用抵抗器１８の両端に発生する電圧を差動増幅
器１９で取出し、差動増幅器１９の出力電圧E1
を電圧比較器２１に与え、電圧比較器２１におい
て正と負の設定した電流値に対応する電圧E2及
び−E3と比較する。これら設定電圧＋E2と−E3
は制御器２からDA変換器２２，２３にデイジタ
ル信号により与えられ、そのデイジタル信号を
DA変換してバツフア増幅器２４，２５から電圧
比較用増幅器２６，２７の各一方の入力端子に与
えられる。 On the other hand, 17 indicates a current limiting circuit. This current limiting circuit 17 is provided for the purpose of preventing a current exceeding an allowable amount from flowing into the device under test 12 and damaging the device. Its structure is such that a current detection resistor 18 is connected in series to the output side of the amplifier 4, the voltage generated across the current detection resistor 18 is extracted by a differential amplifier 19, and the output voltage E 1 of the differential amplifier 19 is
is applied to the voltage comparator 21, and the voltage comparator 21 compares it with the voltages E2 and -E3 corresponding to the positive and negative current values set. These set voltages +E 2 and −E 3
is given as a digital signal from the controller 2 to the DA converters 22 and 23, and the digital signal is
The signals are DA converted and applied from buffer amplifiers 24 and 25 to one input terminal of voltage comparison amplifiers 26 and 27, respectively.
被測定素子１２に流れる電流I0が規定値を越え
たとすると差動増幅器１９の出力電圧E1が＋E2
を越える。これにより増幅器２６の出力電圧は正
極性に反転する。この正極性の電圧を増幅器４の
反転入力端子に与えることにより増幅器４の出力
電圧は共通電位点１６の電位に近い値に強制的に
制御され被測定素子１２に流れる電流I0を制限す
る。一方、DA変換器３から増幅器４を与える電
圧をゼロに戻したとき増幅器４はコンデンサＣに
充電されていた電荷を引き込む。このとき差動増
幅器１９の出力電圧E1は負電圧−E1となる。こ
の負電圧−E1が設定値−E3を越えたとすると増
幅器２７の出力は負電圧を出力する。この負電圧
は増幅器４の反転入力端子に与えられて増幅器４
の出力電圧を共通電位点１６の電位に近ずく方向
に制御する。 If the current I 0 flowing through the device under test 12 exceeds the specified value, the output voltage E 1 of the differential amplifier 19 will be +E 2
exceed. This inverts the output voltage of the amplifier 26 to positive polarity. By applying this positive polarity voltage to the inverting input terminal of the amplifier 4, the output voltage of the amplifier 4 is forcibly controlled to a value close to the potential of the common potential point 16, thereby limiting the current I0 flowing through the device under test 12. On the other hand, when the voltage applied from the DA converter 3 to the amplifier 4 is returned to zero, the amplifier 4 draws the charge stored in the capacitor C. At this time, the output voltage E1 of the differential amplifier 19 becomes a negative voltage -E1 . If this negative voltage -E1 exceeds the set value -E3 , the output of the amplifier 27 outputs a negative voltage. This negative voltage is applied to the inverting input terminal of the amplifier 4.
The output voltage is controlled in a direction closer to the potential of the common potential point 16.
このようにして被測定素子１２に流れる電流が
規定値を越えたとき電流を制限する動作を行なう
ものであるがこの電流制限回路１７を設けたこと
により次のような不都合が生じる。 In this way, when the current flowing through the device under test 12 exceeds a specified value, the current is limited, but the provision of the current limiting circuit 17 causes the following inconvenience.
〈従来の欠点〉
被測定素子１２を試験する方法は被測定素子１
２に所定の一定電圧を与え、そのとき流れる電流
I0が予め規定した範囲に入るか否かを見て被測定
素子１２の良否を判定する。この判定は差動増幅
器１９の出力電圧E1を制御器２に与え、制御器
２に設けた判定手段により行なわれる。<Conventional drawbacks> The method of testing the device under test 12 is
Apply a predetermined constant voltage to 2, and the current flowing at that time
The quality of the device under test 12 is determined by checking whether I 0 falls within a predefined range. This determination is performed by applying the output voltage E 1 of the differential amplifier 19 to the controller 2 and by a determining means provided in the controller 2 .
被測定素子１２を測定端子７と８の間に接続す
る場合、測定端子７と８の間の電圧はゼロの状態
に設定する。被測定端子７と８の間に被測定素子
１２を接続した状態で制御器２はDA変換器３に
デイジタル信号を与え、増幅器４から所定の電圧
を出力させ被測定素子１２に所定の電圧を印加す
る。 When the device under test 12 is connected between the measurement terminals 7 and 8, the voltage between the measurement terminals 7 and 8 is set to zero. With the device under test 12 connected between the terminals 7 and 8 under test, the controller 2 gives a digital signal to the DA converter 3, causes the amplifier 4 to output a predetermined voltage, and outputs a predetermined voltage to the device under test 12. Apply.
制御器２は差動増幅器１９の出力電圧E1を読
込み、その値が良か否かを判定するとDA変換器
３に与えるデイジタル信号をゼロに戻し、次の被
測定素子１２が接続されることを待つ。測定端子
７及び８に被測定素子１２を接続する手段として
は自動機械により行なうか、或は半導体集積回路
の場合リレーによつて構成した切換回路により半
導体集積回路の端子ピンを順次接続する。 The controller 2 reads the output voltage E1 of the differential amplifier 19, and when it determines whether the value is good or not, returns the digital signal given to the DA converter 3 to zero, and connects the next device under test 12. wait. The device to be measured 12 is connected to the measurement terminals 7 and 8 by an automatic machine, or in the case of a semiconductor integrated circuit, the terminal pins of the semiconductor integrated circuit are successively connected by a switching circuit constituted by a relay.
ところで被測定素子１２にはコンデンサＣが含
まれる。この結果増幅器４から電圧を印加すると
きと、印加していた電圧をゼロに戻すとき増幅器
４は出力インピーダンスが充分小さい定電圧源と
して動作するためコンデンサＣに対して大きい充
電電流を供給し、また放電電流を吸引する。この
ため第２図に点線で示すように電圧を印加すると
き流れる充電電流及び電圧をゼロに戻すとき吸引
する放電電流によつて発生する電圧が電流制限値
＋E2と−E3を越えてしまう。 By the way, the device under test 12 includes a capacitor C. As a result, when applying the voltage from the amplifier 4 and returning the applied voltage to zero, the amplifier 4 operates as a constant voltage source with sufficiently small output impedance, so it supplies a large charging current to the capacitor C. Attracts discharge current. For this reason, as shown by the dotted line in Figure 2, the voltage generated by the charging current flowing when voltage is applied and the discharge current drawn when returning the voltage to zero exceeds the current limit values +E 2 and -E 3 . .
このように電圧を印加するとき及び電圧をゼロ
に戻すときに電流制限回路１７が動作してしまう
と増幅器４は電流制限動作を行なつている間定電
流源として動作し、出力インピーダンスは無限大
に近い大きな値となる。このため測定端子７及び
８の電圧変化は第２図に実線で示すように立上り
及び立下りに時間が掛る波形となる。 If the current limiting circuit 17 operates when applying a voltage or returning the voltage to zero in this way, the amplifier 4 operates as a constant current source while performing the current limiting operation, and the output impedance becomes infinite. It becomes a large value close to . Therefore, the voltage changes at the measurement terminals 7 and 8 take a waveform that takes time to rise and fall, as shown by the solid line in FIG.
測定を自動化し高速化しようとした場合、測定
端子７及び８に印加する電圧の立上り及び立下り
に時間が掛ることは障害となる。 When attempting to automate and speed up the measurement, the fact that it takes time for the voltages applied to the measurement terminals 7 and 8 to rise and fall becomes an obstacle.
〈考案の目的〉
この考案は測定端子７及び８の間に印加する電
圧の立上り及び立下りに要する時間を短かくする
ことができる電圧印加電流測定装置を提供しよう
とするものである。<Purpose of the invention> The object of this invention is to provide a voltage applied current measuring device that can shorten the time required for the rise and fall of the voltage applied between the measurement terminals 7 and 8.
〈考案の概要〉
この考案では測定端子に電圧を印加するとき及
び印加していた電圧をゼロに戻すときに電流制限
回路１７の動作を禁止させるように構成したもの
である。<Summary of the invention> This invention is configured to prohibit the operation of the current limiting circuit 17 when applying a voltage to the measurement terminal and when returning the applied voltage to zero.
〈考案の実施例〉
第３図にこの考案の一実施例を示す。全体の回
路構造は第１図とほゞ同じであるからその重複説
明は省略するが、この考案の特徴とする構造は電
流制限回路１７の動作を禁止する手段２８を設
け、この禁止手段２８を測定端子７と８の間に電
圧を印加するときと、ゼロに戻すときに一時的に
動作させ、電流制限回路１７の動作を一時禁止さ
せる構造とした点である。<Example of the invention> Fig. 3 shows an example of the invention. Since the overall circuit structure is almost the same as that shown in FIG. The present invention has a structure in which the current limiting circuit 17 is temporarily activated when applying the voltage between the measurement terminals 7 and 8 and when returning the voltage to zero, and temporarily prohibiting the operation of the current limiting circuit 17.
この例では差動増幅器１９の出力と電圧比較器
２１の間に切換スイツチ２９を接続し、この切換
スイツチ２９によつて禁止手段２８を構成した場
合を示す。切換スイツチ２９は半導体スイツチ素
子によつて構成することができ、常時は電圧比較
器２１の入力端子を差動増幅器１９の出力端子に
接続した状態を維持するが、第４図Ａに示すDA
変換器３にデイジタル信号を与えるタイミング
T1とそのデイジタル信号の値をゼロに戻すタイ
ミングT2に同期して第４図Ｂに示すように切換
スイツチ２９に制御信号Pa，Pbを与え、この制
御信号Pa，Pbを与えている期間電圧比較器２１
の入力端子を共通電位点１６に接続する状態とな
るように制御する。制御信号Pa，Pbは制御器２
から与えることができる。 In this example, a changeover switch 29 is connected between the output of the differential amplifier 19 and the voltage comparator 21, and the changeover switch 29 constitutes the inhibiting means 28. The changeover switch 29 can be constructed by a semiconductor switch element, and normally maintains the state in which the input terminal of the voltage comparator 21 is connected to the output terminal of the differential amplifier 19, but the DA shown in FIG. 4A
Timing of giving digital signal to converter 3
Control signals Pa and Pb are applied to the changeover switch 29 as shown in FIG. 4B in synchronization with the timing T 2 of returning the value of T 1 and its digital signal to zero, and the period during which these control signals Pa and Pb are applied. Voltage comparator 21
control so that the input terminal of is connected to the common potential point 16. Control signals Pa and Pb are controller 2
It can be given from
〈考案の動作〉
上述したこの考案の構造によれば増幅器４の出
力電圧の立上りと立下りに同期して切換スイツチ
２９が共通電位点１６側に切換わる。切換スイツ
チ２９が共通電位点１６側に切換わつている間電
流制限回路１７は機能を停止する。よつて電圧が
立上るときコンデンサＣに充電電流が流れても電
流制限回路１７が制限動作することはない。この
結果増幅器４は本来の定電圧源として動作しコン
デンサＣを急速に充電し、測定端子７と８の間の
電圧を第４図Ｃに実線で示すように高速度に目的
の電圧まで立ち上げることができる。<Operation of the invention> According to the structure of the invention described above, the changeover switch 29 is switched to the common potential point 16 side in synchronization with the rise and fall of the output voltage of the amplifier 4. While the changeover switch 29 is switched to the common potential point 16 side, the current limiting circuit 17 stops functioning. Therefore, even if a charging current flows through the capacitor C when the voltage rises, the current limiting circuit 17 will not perform a limiting operation. As a result, amplifier 4 operates as an original constant voltage source, rapidly charging capacitor C, and rapidly raising the voltage between measurement terminals 7 and 8 to the desired voltage as shown by the solid line in Figure 4C. be able to.
測定端子７と８の間の電圧が所定の電圧まで達
すると信号Paが立下り切換スイツチ２９が差動
増幅器１９側に切換る。切換スイツチ２９が差動
増幅器１９側に転換すると、電流検出用抵抗器１
８に発生する電圧が電圧比較器２１に与えられ電
流値を監視する状態となる。またこのとき制御器
２は差動増幅器１９の出力電圧を取込み、被測定
素子１２に所定の電圧を与えたとき流れる電流値
が設定された範囲に入るか否かを判定する。判定
動作が終了すると制御器２はDA変換器３に与え
ているデイジタル信号をゼロに戻し、測定端子７
及び８に印加している電圧をゼロに戻す。これと
共に制御信号Pbを出力し、切換スイツチ２９を
共通電位側に切換る。よつて電圧が立下るときコ
ンデンサＣに充電された電荷を増幅器４が吸引
し、そのとき流れる放電電流が設定値−E3で決
まる電流値を越えても電流制限回路１７は制限動
作を禁止する。よつて電圧の立下りは第４図Ｃに
実線で示すように高速度でゼロに戻る。 When the voltage between the measurement terminals 7 and 8 reaches a predetermined voltage, the signal Pa falls and the switch 29 switches to the differential amplifier 19 side. When the changeover switch 29 switches to the differential amplifier 19 side, the current detection resistor 1
The voltage generated at 8 is applied to the voltage comparator 21, and the current value is monitored. Also, at this time, the controller 2 takes in the output voltage of the differential amplifier 19 and determines whether the current value that flows when a predetermined voltage is applied to the device under test 12 falls within a set range. When the judgment operation is completed, the controller 2 returns the digital signal given to the DA converter 3 to zero, and the measurement terminal 7
and the voltage applied to 8 is returned to zero. At the same time, a control signal Pb is output, and the changeover switch 29 is switched to the common potential side. Therefore, when the voltage falls, the amplifier 4 absorbs the charge stored in the capacitor C, and even if the discharge current flowing at that time exceeds the current value determined by the set value -E3 , the current limiting circuit 17 prohibits the limiting operation. . Therefore, the fall of the voltage returns to zero at a high speed, as shown by the solid line in FIG. 4C.
〈考案の効果〉
上述したようにこの考案によれば被測定素子１
２に印加する電圧の立上り及び立下りを短時間に
行なわせることができる。よつて被測定素子１２
の測定時間を短かくすることができるため被試験
素子１２を大量に検査する自動検査装置に適用し
てその効果は大である。<Effect of the invention> As mentioned above, according to this invention, the device under test 1
The rise and fall of the voltage applied to 2 can be performed in a short time. Therefore, the device under test 12
Since the measuring time can be shortened, the present invention can be applied to an automatic inspection apparatus that inspects a large number of devices under test 12, and has a great effect.
〈考案の変形実施例〉
上述ではスイツチ２９によつて電流制限回路１
７のループを開放して動作を禁止させたが、一時
的にDA変換器２２，２３に設定する数値を大き
くして充電電流及び放電電流に対して電流制限回
路１７が応動しないように構成することもでき
る。<Modified embodiment of the invention> In the above, the current limiting circuit 1 is controlled by the switch 29.
7 loop was opened to prohibit the operation, but the values set in the DA converters 22 and 23 were temporarily increased so that the current limiting circuit 17 would not respond to the charging current and discharging current. You can also do that.
また制御器に制御信号Pa，Pbの発生を禁止す
る手段を設けることも考えられる。つまり被測定
素子によつては回路の配線導体の電流容量により
大きな電流を流すことができないものもある。こ
のような素子を試験する場合には従来通り、電流
制限回路１７を作動させて時間を掛けて所定の電
圧まで上昇させ、また電圧を立下げるようにすれ
ばよい。 It is also conceivable to provide the controller with means for prohibiting the generation of control signals Pa and Pb. In other words, some devices under test cannot allow a large current to flow due to the current capacity of the wiring conductors of the circuit. When testing such an element, the current limiting circuit 17 may be activated to increase the voltage to a predetermined voltage over time, and then the voltage may be lowered, as in the conventional manner.
第１図は従来の電圧印加電流測定装置を説明す
るための接続図、第２図は従来の電圧印加電流測
定装置の動作を説明するための波形図、第３図は
この考案の一実施例を説明するための接続図、第
４図はこの考案の動作を説明するための波形図で
ある。
１：定電圧源、２：制御器、３：DA変換器、
４：増幅器、５，６，９，１０：ケーブル、１
１：ボルテージフオロワ、１２：被測定素子、１
３，１４：電源、１５：電源の共通電位点、１
６：回路の共通電位点、１７：電流制限回路、１
８：電流検出用抵抗器、１９：差動増幅器、２
１：電圧比較器、２２，２３：DA変換器、２
４，２５：バツフア増幅器、２６，２７：電圧比
較用増幅器、２８：電流制限回路の動作を禁止さ
せる手段。
Fig. 1 is a connection diagram for explaining the conventional voltage applied current measuring device, Fig. 2 is a waveform diagram for explaining the operation of the conventional voltage applied current measuring device, and Fig. 3 is an example of an embodiment of this invention. FIG. 4 is a waveform diagram for explaining the operation of this invention. 1: Constant voltage source, 2: Controller, 3: DA converter,
4: Amplifier, 5, 6, 9, 10: Cable, 1
1: Voltage follower, 12: Device under test, 1
3, 14: Power supply, 15: Common potential point of power supply, 1
6: Common potential point of the circuit, 17: Current limiting circuit, 1
8: Current detection resistor, 19: Differential amplifier, 2
1: Voltage comparator, 22, 23: DA converter, 2
4, 25: buffer amplifier, 26, 27: voltage comparison amplifier, 28: means for inhibiting the operation of the current limiting circuit.
Claims (1)
と、 Ｂ この定電圧源から被測定素子に流れる電流を
監視し、設定した電流値を越えたとき上記被測
定素子に流入する電流を制限する電流制限手段
と、 Ｃ 上記定電圧源から上記被測定素子に電圧を印
加するタイミング及び被測定素子に印加した電
圧を除去するタイミングにおいて上記電流制限
手段が制限動作することを禁止する手段と、 を具備して成る電圧印加電流測定装置。[Claims for Utility Model Registration] A. A constant voltage source that applies a constant voltage to the device under test; B. The current flowing from this constant voltage source to the device under test is monitored, and when the current value exceeds a set value, the device under test is C current limiting means for limiting the current flowing into the element; C; the current limiting means performs a limiting operation at the timing of applying a voltage from the constant voltage source to the device under test and at the timing of removing the voltage applied to the device under test; A voltage applied current measuring device comprising: a means for prohibiting the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1563384U JPS60127572U (en) | 1984-02-06 | 1984-02-06 | Voltage applied current measuring device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1563384U JPS60127572U (en) | 1984-02-06 | 1984-02-06 | Voltage applied current measuring device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60127572U JPS60127572U (en) | 1985-08-27 |
| JPS641649Y2 true JPS641649Y2 (en) | 1989-01-13 |
Family
ID=30501651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1563384U Granted JPS60127572U (en) | 1984-02-06 | 1984-02-06 | Voltage applied current measuring device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60127572U (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6914425B2 (en) * | 2003-04-29 | 2005-07-05 | Teradyne, Inc. | Measurement circuit with improved accuracy |
| US7271610B2 (en) * | 2004-12-17 | 2007-09-18 | Teradyne, Inc. | Using a parametric measurement unit to sense a voltage at a device under test |
| US7403030B2 (en) * | 2004-12-17 | 2008-07-22 | Teradyne, Inc. | Using parametric measurement units as a source of power for a device under test |
| JP4753897B2 (en) * | 2007-02-27 | 2011-08-24 | 株式会社リコー | Measuring method of semiconductor device |
-
1984
- 1984-02-06 JP JP1563384U patent/JPS60127572U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60127572U (en) | 1985-08-27 |
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