JPS5862575A - Testing of semiconductor integrated circuit - Google Patents
Testing of semiconductor integrated circuitInfo
- Publication number
- JPS5862575A JPS5862575A JP56161725A JP16172581A JPS5862575A JP S5862575 A JPS5862575 A JP S5862575A JP 56161725 A JP56161725 A JP 56161725A JP 16172581 A JP16172581 A JP 16172581A JP S5862575 A JPS5862575 A JP S5862575A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- capacitor
- circuit
- large capacity
- charging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、アナログ信号処理用の電子回路を１１１−の
半導体基板内へ集積化した半導体集積回路の交流緒特性
を高速で測定する試験方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a test method for rapidly measuring the AC characteristics of a semiconductor integrated circuit in which an electronic circuit for analog signal processing is integrated into a semiconductor substrate 111-.
かかる半導体集積回路（以下被試験集積回路と記す）の
交流緒特性を測定するにあたり、従来被試験集積回路の
周辺に大容量のコンデンサを付加する場合があった。こ
のコンデンサは、直流電圧阻止交流信号通過、異常発振
の防止、リップル除去などさまざまな目的に沿って付加
されている。In measuring the alternating current characteristics of such a semiconductor integrated circuit (hereinafter referred to as an integrated circuit under test), a large capacitance capacitor has conventionally been added around the integrated circuit under test. This capacitor is added for various purposes such as blocking DC voltage, passing AC signals, preventing abnormal oscillations, and removing ripples.
第１図は従来の交流緒特性の試験回路の構成例を示す図
であり、図中１は被試験集積回路、２は大容量の入力コ
ンデンサ、３は交流測定信号源、４は大容量のコンデン
サ、６は被試験集積回路用直流電源、６は直流電源用ス
イッチそして７は交流出力測定器である。Figure 1 is a diagram showing an example of the configuration of a conventional test circuit for AC characteristics. A capacitor, 6 a DC power source for the integrated circuit under test, 6 a DC power switch, and 7 an AC output measuring device.
以上のように構成された試験回路の直流電源用スイッチ
６を閉成することによって被試験集積回路１へ所定の直
流電圧を印加するとともに、交流測定信号源３から交流
測定信号を供給して交流特性を測定する場合、コンデン
サ２と４の接続される。被試験集積回路の端子の抵抗が
高くコンデンサの充電々流が小さいと、時定数（ＣＲ時
定数）が極めて大きくなる。このため、交流諸慣性の測
定Ｑ［、コンデンサ２および４への充電が兄１’Ｌ、被
試験集積回路１が安定状態に達し／このちに行わねＱ、
１］ならなかった。勿論、−に述した端５′のり（抗が
比較的低い場合であっても、コンデンサが大芥；１トで
あるとやはり充電時定数は大きくなる。、このように、
従来の試験回路を用いた場合には、試験作業時間の中に
待期のだめの時間が占める割合が大きく、このため高速
の測定が困難であり、作業能率の低下は避けられなかっ
／こ。By closing the DC power switch 6 of the test circuit configured as described above, a predetermined DC voltage is applied to the integrated circuit under test 1, and an AC measurement signal is supplied from the AC measurement signal source 3. When measuring characteristics, capacitors 2 and 4 are connected. If the terminal resistance of the integrated circuit under test is high and the charging current of the capacitor is small, the time constant (CR time constant) becomes extremely large. Therefore, measurement of AC inertia Q[, charging of capacitors 2 and 4 is 1'L, integrated circuit under test 1 has reached a stable state/will be carried out soonQ,
1] was not achieved. Of course, even if the resistance at the end 5' described in - is relatively low, if the capacitor is large, the charging time constant will still be large.In this way,
When conventional test circuits are used, waiting time occupies a large proportion of the test work time, making high-speed measurements difficult and inevitably reducing work efficiency.
本発明は、以−［説明してきた従来の試験回路に存在し
た不都合の排除を意図してなされたものであり、本発明
の試験方法の特徴は、大容量コンデンサを大容量ならび
に小容量のコンデンサに分割し１、直流電源印加時には
被試験集積回路に小芥駄のコンデンサをｆ＝Ｊ加して・
回′路が異常状態に陥いることを抑え、同時に大容量の
コンデンサを被試験集積回路とは異るコンデンサ充電器
で急速充電し７、充′１１Ｌの完了したコンデンサを被
試験集積回路′＼接続する方法を採ることによって高速
測定を可能としたところにある。The present invention has been made with the intention of eliminating the inconveniences that existed in the conventional test circuits described above, and the characteristics of the test method of the present invention are to 1. When applying DC power, add a small capacitor f = J to the integrated circuit under test.
To prevent the circuit from falling into an abnormal state, at the same time, a large capacitor is quickly charged with a capacitor charger different from that of the integrated circuit under test. By using a connecting method, high-speed measurements are possible.
以下に本発明の試験方法を可能にする試験回路の構成を
示す第２図を参照して本発明について詳しく説明する。The present invention will be described in detail below with reference to FIG. 2, which shows the configuration of a test circuit that enables the test method of the present invention.
図示するように、本発明の試験方法で採用する試験回路
では、第１図で示した大容量コンデンサ２と４にかわっ
て大容量コンデンサ２′と小容量コンデンサ８ならびに
大容量コンデンサ４′と９が準備され、また、大容量コ
ンデンサ２′と４′は回路切換器１０と１１を介して小
容量コンデンサ８と９とに並列に接続出来る関係で配置
され、さらに大容量コンデンサ２′と４′には小容量コ
ンデンサ８と９が接続される被試験集積回路の端子電圧
を正確に検出して急速に充電する高入力抵抗の増幅器よ
シなる充電回路１２．１３を接続した構成が採られてい
る。As shown in the figure, in the test circuit employed in the test method of the present invention, instead of the large capacitors 2 and 4 shown in FIG. are prepared, and the large capacitors 2' and 4' are arranged in such a way that they can be connected in parallel to the small capacitors 8 and 9 via circuit switches 10 and 11, and the large capacitors 2' and 4' A configuration is adopted in which a charging circuit 12.13 such as an amplifier with a high input resistance is connected to accurately detect the terminal voltage of the integrated circuit under test to which small capacitance capacitors 8 and 9 are connected and rapidly charge it. There is.
本発明では、か）・る構成の試験回路を用い、以下のよ
うにして被試験集積回路の交流諸特性の測定が行われる
。先ず、従来と同様、直流電源用スイッチ６を閉成して
被試験集積回路用電源６から被試験集積回路１に所定の
電源電圧Ｖｃｃを印加する。この電源電圧Ｖｃｃの印加
時には回路切換器１゜と１１は図示する接点を選択して
いる。このため大容量のコンデンサ２′と４′は被試験
集積回路１には接続されてはおらず、小容量のコンデン
サ８′と９のみが接続されるところとなり、これらの小
容量コンデンサによシ試験回路の異常発振などの異常状
態に陥いることを防いでいる。ところで、充電回路１２
と１３は電源投入直後における被試験集積回路１の端子
電圧を検出し、被試験集積回路１が安定状態となるレベ
ルまで大容量コンデンサ２′と４′を急速に充電する。In the present invention, the AC characteristics of the integrated circuit under test are measured in the following manner using the test circuit having the above configuration. First, as in the conventional case, the DC power supply switch 6 is closed and a predetermined power supply voltage Vcc is applied from the power supply 6 for the integrated circuit under test to the integrated circuit under test 1. When this power supply voltage Vcc is applied, the circuit switches 1° and 11 select the contacts shown in the figure. Therefore, large capacity capacitors 2' and 4' are not connected to the integrated circuit under test 1, and only small capacity capacitors 8' and 9 are connected. This prevents abnormal conditions such as abnormal oscillation of the circuit. By the way, the charging circuit 12
and 13 detect the terminal voltage of the integrated circuit under test 1 immediately after the power is turned on, and rapidly charge the large capacitors 2' and 4' to a level at which the integrated circuit under test 1 is in a stable state.
このようにして大容量コンデンサ２′と４′の充電が完
了したのち、回路切換器１ｏと１１を働かせることによ
υ大容量コンデンサ２′と４′を被試験集積回路１の端
子へ接続する。コンデンサ８と２′ならびに９と４′は
第１図で示した大容量コンデンサを分割したものである
ため、上記の動作で被試験集積回路１の端子には第１図
で示した大容量コンデンサ２ならびに４と等しい容址値
をもち、しかも充電の完了したコンデンサが接続される
。次いで、交流出力測定器７を用いて交流諸特性の測定
をなすことにより、本発明にかかる試験が完了する。After the charging of the large capacity capacitors 2' and 4' is completed in this way, the circuit switches 1o and 11 are activated to connect the υ large capacity capacitors 2' and 4' to the terminals of the integrated circuit under test 1. . Since capacitors 8 and 2' and 9 and 4' are divided large-capacity capacitors shown in FIG. 1, the large-capacity capacitors shown in FIG. Capacitors having capacitance values equal to 2 and 4, and which are fully charged, are connected. Next, the test according to the present invention is completed by measuring various AC characteristics using the AC output measuring device 7.
なお、充電器１２と１３は被試験集積回路１とは高抵抗
接続されているため、試験回路の交流特性には何等の影
響も及ぼさない。、
以上説明したところから明らかなように、本発明の試験
方法によれば、大容量コンデンサを被試験集積回路を介
すことなく急速に充電し、充電完了後にこれを被試験集
積回路に接続することによって被試験集積回路を安定状
態としているため、極めて速い測定が可能となシ、試験
作業の能率を著しく高めることのできる効果が奏される
。Note that since the chargers 12 and 13 are connected to the integrated circuit under test 1 with high resistance, they do not have any influence on the AC characteristics of the test circuit. As is clear from the above explanation, according to the test method of the present invention, a large capacity capacitor is rapidly charged without going through the integrated circuit under test, and after charging is completed, it is connected to the integrated circuit under test. As a result, the integrated circuit under test is kept in a stable state, making it possible to perform extremely fast measurements and significantly increasing the efficiency of test work.
第１図は従来の被試験集積回路の交流特性を測定する代
表的な回路図、第２図は本発明にかかる交流特性の試験
方法を可能にする代表的な回路例を示す図である。
１・・・・・・被試験集積回路、２・・・・・・大容量
コンデンザ、３・・・・・・交流測定信号源、４・・・
・・・犬容ｔ、＋＝コ／デンザ、５・・・・・・被試験
集積回路用直流電源、６・・・・的流電源用スイッチ、
７・・・・・・交流出力測定器、８゜９・・・・・・分
割小容１１：：コンデンサ、２’、４’・・・・・分割
人界ｉ＋：：コンデンサ、１０．１１・・・・・・回路
切換器、１２．１３・・・・・・被試験集積回路端子電
圧検出用高入力抵抗増幅器よりなる大容叶コンデンサ充
電Ｈ路、FIG. 1 is a typical circuit diagram for measuring the AC characteristics of a conventional integrated circuit under test, and FIG. 2 is a diagram showing a typical circuit example that enables the AC characteristics testing method according to the present invention. 1... Integrated circuit under test, 2... Large capacity capacitor, 3... AC measurement signal source, 4...
...Dog capacity t, +=co/denza, 5...DC power supply for the integrated circuit under test, 6... Switch for target current power supply,
7...AC output measuring device, 8゜9...Divided small capacity 11:: Capacitor, 2', 4'......Divided human world i+:: Capacitor, 10.11 ......Circuit switch, 12.13......Large capacity capacitor charging H path consisting of a high input resistance amplifier for detecting terminal voltage of the integrated circuit under test,
Claims (1)
体集積回路の交流特性を試験するにあたり１１１に耐大
容量コンデンサを小容量コンデンサと人界（１ｊ：コン
デンサとに分割し、四分割小容量コンデ／ツを前記半導
体集積回路の前記外部接続端子へ接続した状態で動作電
圧を印加し、さらに前記分割大容星コンデンサを回路切
換器を介して前記外部接続端子へ接続ＩＪＪ能な関係で
配設するとともに動イ′１電圧印加直後には前記外部端
子への接続を断ち同外部端子の′電圧を検出する高入力
抵抗増幅２非よりなる充電回路で急速充電し、次いで充
電完了゛）み分割大容鍛コンデンサを前記外部接続端子
へＶぎ前記半導体集積回路を安定状態に設定することを
１１徴とする半導体集積回路の試験方法。When testing the AC characteristics of a semiconductor integrated circuit in which a large capacity capacitor is connected to a predetermined external terminal, the large capacity capacitor is divided into a small capacity capacitor and a human world (1j: capacitor), and the small capacity capacitor is divided into four parts. /T is connected to the external connection terminal of the semiconductor integrated circuit and an operating voltage is applied, and the divided large capacity star capacitor is further connected to the external connection terminal via a circuit switch and arranged in an IJJ-enabled relationship. At the same time, immediately after the voltage is applied, the connection to the external terminal is cut off, and a charging circuit consisting of a high input resistance amplifier 2 that detects the voltage at the external terminal performs rapid charging, and then charging is completed. 11. A method for testing a semiconductor integrated circuit, the eleventh feature of which is to set the semiconductor integrated circuit in a stable state by connecting a large capacity forged capacitor to the external connection terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56161725A JPS5862575A (en) | 1981-10-09 | 1981-10-09 | Testing of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56161725A JPS5862575A (en) | 1981-10-09 | 1981-10-09 | Testing of semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5862575A true JPS5862575A (en) | 1983-04-14 |
| JPH0228833B2 JPH0228833B2 (en) | 1990-06-26 |
Family
ID=15740690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56161725A Granted JPS5862575A (en) | 1981-10-09 | 1981-10-09 | Testing of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5862575A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6350072U (en) * | 1986-09-20 | 1988-04-05 |
-
1981
- 1981-10-09 JP JP56161725A patent/JPS5862575A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6350072U (en) * | 1986-09-20 | 1988-04-05 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0228833B2 (en) | 1990-06-26 |
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