JPS6413166U - - Google Patents

Info

Publication number
JPS6413166U
JPS6413166U JP1987107387U JP10738787U JPS6413166U JP S6413166 U JPS6413166 U JP S6413166U JP 1987107387 U JP1987107387 U JP 1987107387U JP 10738787 U JP10738787 U JP 10738787U JP S6413166 U JPS6413166 U JP S6413166U
Authority
JP
Japan
Prior art keywords
substrate
emitting device
light emitting
current limiting
led
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987107387U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987107387U priority Critical patent/JPS6413166U/ja
Publication of JPS6413166U publication Critical patent/JPS6413166U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Description

【図面の簡単な説明】
第1図ないし第5図は本考案によるLED発光
装置の実施例を示すもので、第1図は第1実施例
の断面図、第2図は第1図の平面図、第3図は第
1図の底面図、第4図は電気回路図、第5図は第
2実施例の断面図、第6図は特性図である。1…
…基板、2……表面、3……接続線、4……LE
Dチツプ搭載部、5……金パツド、6……接続部
、7……LED、8……リード線、9……スルー
ホール、10……裏面、11……接続線、12…
…電流制限抵抗、13……接続部、14……電源
、15,16……端子。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 複数個のLEDを基板上に配置してなる発
    光装置において、前記LEDと電流制限抵抗との
    直列回路を2個以上並列に接続し、前記電流制限
    抵抗をトリミングすることによつてその抵抗値を
    調節し目的の発光強度を得るようにしたことを特
    徴とするLED発光装置。 (2) 基板はセラミツク基板とし、この基板に厚
    膜印刷によつて配線および制限抵抗を形成し、L
    EDチツプを搭載したことを特徴とする実用新案
    登録請求の範囲第1項記載のLED発光装置。 (3) 基板はPCBを用い、電流制限抵抗はチツ
    プ抵抗を用いてモールドタイプLEDを搭載した
    ことを特徴とする実用新案登録請求の範囲第1項
    記載のLED発光装置。 (4) LEDと電流制限抵抗は基板の表裏に別々
    に設けたことを特徴とする実用新案登録請求の範
    囲第1項記載のLED発光装置。
JP1987107387U 1987-07-13 1987-07-13 Pending JPS6413166U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987107387U JPS6413166U (ja) 1987-07-13 1987-07-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987107387U JPS6413166U (ja) 1987-07-13 1987-07-13

Publications (1)

Publication Number Publication Date
JPS6413166U true JPS6413166U (ja) 1989-01-24

Family

ID=31341753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987107387U Pending JPS6413166U (ja) 1987-07-13 1987-07-13

Country Status (1)

Country Link
JP (1) JPS6413166U (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007129062A (ja) * 2005-11-04 2007-05-24 Koa Corp Led光源装置
US7286148B2 (en) 2004-02-10 2007-10-23 Seiko Epson Corporation Line head and image forming apparatus incorporating the same
JP2013143372A (ja) * 2012-01-06 2013-07-22 Lextar Electronics Corp 照明回路及びそれを備える照明装置
JP2021148310A (ja) * 2020-03-16 2021-09-27 株式会社富士通ゼネラル 空気調和機

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7286148B2 (en) 2004-02-10 2007-10-23 Seiko Epson Corporation Line head and image forming apparatus incorporating the same
JP2007129062A (ja) * 2005-11-04 2007-05-24 Koa Corp Led光源装置
JP2013143372A (ja) * 2012-01-06 2013-07-22 Lextar Electronics Corp 照明回路及びそれを備える照明装置
JP2021148310A (ja) * 2020-03-16 2021-09-27 株式会社富士通ゼネラル 空気調和機

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