JPS6321038U - - Google Patents
Info
- Publication number
- JPS6321038U JPS6321038U JP11353886U JP11353886U JPS6321038U JP S6321038 U JPS6321038 U JP S6321038U JP 11353886 U JP11353886 U JP 11353886U JP 11353886 U JP11353886 U JP 11353886U JP S6321038 U JPS6321038 U JP S6321038U
- Authority
- JP
- Japan
- Prior art keywords
- hole
- led
- array
- insulating substrate
- array head
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Laser Beam Printer (AREA)
- Exposure Or Original Feeding In Electrophotography (AREA)
- Dot-Matrix Printers And Others (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
Description
第1図は本考案の一実施例によるLEDアレイ
ヘツドの概略的断面構成を示す図、第2図は本考
案の他の実施例を示す図、第3図は従来のLED
アレイヘツドの概略的断面構成を示す図、第4図
はLEDアレイヘツドの基本的な回路構成を示す
図である。 図において、3はLEDアレイチツプ、9はス
ルーホール、21は支持基板、1は支持基体、5
4は裏面電極、51は導体パターン、91は導電
性部材である。
ヘツドの概略的断面構成を示す図、第2図は本考
案の他の実施例を示す図、第3図は従来のLED
アレイヘツドの概略的断面構成を示す図、第4図
はLEDアレイヘツドの基本的な回路構成を示す
図である。 図において、3はLEDアレイチツプ、9はス
ルーホール、21は支持基板、1は支持基体、5
4は裏面電極、51は導体パターン、91は導電
性部材である。
Claims (1)
- 【実用新案登録請求の範囲】 (1) 絶縁基板上に複数のLEDアレイヘツドと
そのドライバICとを搭載し、 LEDアレイチツプ配置部の導体パターンと上
記絶縁基板の裏面導体とを電気的に接続するため
のスルーホールを設けてなることを特徴とするL
EDアレイヘツド。 (2) 上記絶縁基板は、導電性支持基体上に搭載
されていることを特徴とする実用新案登録請求の
範囲第1項記載のLEDアレイヘツド。 (3) 上記スルーホールは、LEDチツプアレイ
直下以外の位置に設けられていることを特徴とす
る実用新案登録請求の範囲第1項または第2項記
載のLEDアレイヘツド。 (4) 上記スルーホールは、LEDチツプアレイ
直下に設けられており、その内部には導電性部材
が、当該スルーホールによる開口面が平坦になる
ように充填されていることを特徴とする実用新案
登録請求の範囲第1項または第2項記載のLED
アレイヘツド。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11353886U JPS6321038U (ja) | 1986-07-23 | 1986-07-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11353886U JPS6321038U (ja) | 1986-07-23 | 1986-07-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6321038U true JPS6321038U (ja) | 1988-02-12 |
Family
ID=30995439
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11353886U Pending JPS6321038U (ja) | 1986-07-23 | 1986-07-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6321038U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63176164A (ja) * | 1987-01-16 | 1988-07-20 | Agency Of Ind Science & Technol | 駆動装置 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58130581A (ja) * | 1982-01-29 | 1983-08-04 | Toshiba Corp | デイスプレイ装置 |
-
1986
- 1986-07-23 JP JP11353886U patent/JPS6321038U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58130581A (ja) * | 1982-01-29 | 1983-08-04 | Toshiba Corp | デイスプレイ装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63176164A (ja) * | 1987-01-16 | 1988-07-20 | Agency Of Ind Science & Technol | 駆動装置 |