JPS6342859B2 - - Google Patents
Info
- Publication number
- JPS6342859B2 JPS6342859B2 JP55101130A JP10113080A JPS6342859B2 JP S6342859 B2 JPS6342859 B2 JP S6342859B2 JP 55101130 A JP55101130 A JP 55101130A JP 10113080 A JP10113080 A JP 10113080A JP S6342859 B2 JPS6342859 B2 JP S6342859B2
- Authority
- JP
- Japan
- Prior art keywords
- plating layer
- tab
- silver
- pellet
- silver plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 39
- 229910052709 silver Inorganic materials 0.000 claims description 39
- 239000004332 silver Substances 0.000 claims description 39
- 238000007747 plating Methods 0.000 claims description 35
- 239000008188 pellet Substances 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 17
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 239000010970 precious metal Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000005496 eutectics Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に、リードフ
レームの改良技術に係り、例えば、半導体を用い
た集積回路装置（以下、ICということがある。）
に利用して有効な技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to semiconductor devices, and in particular to lead frame improvement techniques, such as integrated circuit devices (hereinafter sometimes referred to as ICs) using semiconductors. )
Concerning effective techniques that can be used.
一般に、ICの如き半導体装置の製造には、金
属リボン状のリードフレームが用いられている。
このリードフレームは集積回路が作りこまれた半
導体ペレツト（以下、ペレツトという。）を取り
付けるためのタブ、ペレツトのボンデイングパツ
ドとワイヤで電気的に接続されるインナリード、
該インナリードとタブと呼ばれる連結部を介して
連結され、外部接続端子を構成するアウタリード
等を有している。
Generally, metal ribbon-shaped lead frames are used in the manufacture of semiconductor devices such as ICs.
This lead frame includes a tab for attaching a semiconductor pellet (hereinafter referred to as a pellet) into which an integrated circuit is built, an inner lead that is electrically connected to the pellet's bonding pad by wire, and
It has an outer lead, etc., which is connected to the inner lead via a connecting part called a tab and constitutes an external connection terminal.
従来、このようなリードフレームにおいて、イ
ンナリードにはペレツトのボンデイングパツドと
の電気的接続のために銀（Ag）メツキ層が、樹
脂モールドや、セラミツクパツケージの如き封入
物への気密封止のためのモールド外形線（第１図
のML参照）、またはガラス封止外形の領域内で
銀メツキ加工により形成されている。 Conventionally, in such a lead frame, the inner lead has a silver (Ag) plating layer for electrical connection with the bonding pad of the pellet, and a layer of silver (Ag) plating is used for hermetically sealing the resin mold or the enclosure such as a ceramic package. It is formed by silver plating within the mold outline (see ML in Figure 1) or the area of the glass sealing outline.
しかしながら、リードフレームに形成される銀
メツキ層は部分メツキされる場合でも、殆どのメ
ツキ部分が本来不必要なものであるため、きわめ
て高価な貴金属材料である銀の無駄使いになり、
徒らにリードフレームおよびそれを用いた半導体
装置のコストを上昇させる結果となる。
However, even when the silver plating layer formed on the lead frame is partially plated, most of the plating parts are originally unnecessary, resulting in a waste of silver, which is an extremely expensive precious metal material.
This unnecessarily increases the cost of the lead frame and the semiconductor device using the lead frame.
さらに、銀の場合には、本来タブには銀メツキ
層を形成する必要がない上に、余分な銀メツキに
よりマイグレーシヨンのポテンシヤルを高くし、
水分による短絡を生じ易くなるという問題点があ
ることが、本発明者によつて明らかにされた。 Furthermore, in the case of silver, it is not necessary to form a silver plating layer on the tab, and the extra silver plating increases the migration potential.
The present inventor has revealed that there is a problem in that short circuits are likely to occur due to moisture.
本発明は前記した従来技術の欠点を解消するた
めになされたもので、貴金属材料である銀の使用
量を大幅に減少させることができるとともに、銀
によるマイグレーシヨンを防止することができる
半導体装置を提供することを目的とするものであ
る。 The present invention has been made in order to eliminate the drawbacks of the prior art described above, and provides a semiconductor device that can significantly reduce the amount of silver used as a precious metal material and can prevent migration due to silver. The purpose is to provide
本発明の前記ならびにその他の目的と新規な特
微は、本明細書の記述および添付図面から明らか
になるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なも
のの概要を説明すれば、次の通りである。
An overview of typical inventions disclosed in this application is as follows.
すなわち、インナリードのワイヤボンデイング
に必要な部分にのみ銀メツキ層が形成されている
インナリードフレームを使用し、該リードフレー
ムの非銀メツキ形成層であるタブ上にペレツトを
ボンデイングするとともに、このペレツトの電極
部に一端がボンデイングされたワイヤの他端を前
記部分銀メツキ層にボンデイングし、これらイン
ナリード、ペレツト、タブおよびワイヤをパツケ
ージにより封止したものである。 That is, an inner lead frame is used in which a silver plating layer is formed only in the portions necessary for wire bonding of the inner lead, and a pellet is bonded onto the tab, which is a non-silver plating layer of the lead frame, and this pellet is One end of the wire is bonded to the electrode portion of the wire, and the other end of the wire is bonded to the partial silver plating layer, and these inner leads, pellets, tabs, and wires are sealed with a package.
前記した手段によれば、銀のメツキ層が形成さ
れる領域はリードにおいてワイヤボンデイングが
実施されるきわめて僅かな局所にすぎないため、
貴金属材料である銀の使用量は大幅に減少される
ことになる。
According to the above-mentioned means, since the area where the silver plating layer is formed is only a very small local area in the lead where wire bonding is performed,
The amount of silver used as a precious metal material will be significantly reduced.
また、ペレツトがボンデイングされるタブには
銀メツキ層が形成されないため、銀によるマイグ
レーシヨンは防止されることになる。 Further, since no silver plating layer is formed on the tab to which the pellet is bonded, migration due to silver is prevented.
第１図は本発明の一実施例である半導体装置に
使用されているリードフレームを示す平面図、第
２図はそのペレツト取付状態を示す拡大部分断面
図、第３図は本発明の他の実施例におけるペレツ
ト取付状態を示す拡大部分断面図、第４図は本発
明の一実施例である半導体装置を示す斜視図であ
る。
FIG. 1 is a plan view showing a lead frame used in a semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged partial sectional view showing a state in which a pellet is attached, and FIG. FIG. 4 is an enlarged partial cross-sectional view showing a state in which pellets are attached in an embodiment, and FIG. 4 is a perspective view showing a semiconductor device according to an embodiment of the present invention.
本実施例において、半導体装置はシングル・イ
ン・ライン形樹脂封止パツケージを備えている
IC（以下、SIP・ICということがある。）として構
成されており、このSIP・ICは第１図および第２
図に示されているようなリードフレームが使用さ
れて製造されている。 In this embodiment, the semiconductor device is equipped with a single-in-line resin-sealed package.
It is configured as an IC (hereinafter sometimes referred to as SIP-IC), and this SIP-IC is shown in Figures 1 and 2.
It is manufactured using a lead frame as shown in the figure.
第１図および第２図には樹脂封止パツケージを
成形される前におけるリードフレームが示されて
おり、このリードフレームは、外部接続端子を構
成するアウタリード１０、該アウタリード１０と
連結部（ダム）１２を介して連結されたインナリ
ード１４、集積回路が作り込まれているペレツト
１８（第２図）を取り付けるタブ１６、該タブ１
６を機械的に支持するタブ吊り用リード２０、前
記ペレツト１８のボンデイングパツド部と前記イ
ンナリード１４とを電気的に接続するワイヤ２２
（第２図）を有している。 1 and 2 show the lead frame before the resin-sealed package is molded. Inner lead 14 connected via 12, tab 16 for attaching pellet 18 (FIG. 2) in which an integrated circuit is fabricated, said tab 1
6, a wire 22 that electrically connects the bonding pad portion of the pellet 18 and the inner lead 14.
(Fig. 2).
本実施例においては、前記インナリード１４に
は銀からなる銀メツキ層２４がワイヤ２２をボン
デイングすべき部分にのみ配されて部分的に形成
されている。したがつて、本実施例においては、
貫金属である銀の使用量は非常に少なくなり、コ
スト的にきわめて有利になる。 In this embodiment, a silver plating layer 24 made of silver is partially formed on the inner lead 14 only in the area where the wire 22 is to be bonded. Therefore, in this example,
The amount of silver, which is a solid metal, used becomes extremely small, making it extremely advantageous in terms of cost.
このような部分的な銀メツキ層２４を形成する
方法としては、まず第１に、銀メツキ層を形成す
べき部分のみを除いてリードフレームにマスキン
グをした状態でメツキ加工を施すスポツトメツキ
式の方法が挙げられる。 As a method for forming such a partial silver plating layer 24, firstly, there is a spot plating method in which plating is performed with the lead frame masked except for only the portion where the silver plating layer is to be formed. can be mentioned.
第２の方法としては、ノズルを必要な部分だけ
につけるメツキ電極式の方法が考えられる。 A second method is a plating electrode method in which the nozzle is attached only to the necessary areas.
このようにして、インナリード１４上の必要な
部分のみに形成された銀メツキ層２４には、他端
をペレツト１８のボンデイングパツド部にボンデ
イングされたワイヤ２２の一端がボンデイングさ
れており、この銀メツキ層２４とワイヤ２２との
ボンデイングにより良好な電気的接続が行われ
る。なお、その場合、銀メツキ層２４はごく一部
のみに施されているので、インナリード１４のほ
ぼ全面に銀メツキ層を施す場合と違つて、銀メツ
キ層２４に若干のだれが生じても特に問題とはな
らないし、ボンダビリテイーもきわめて良好にな
る。 In this way, one end of the wire 22, the other end of which is bonded to the bonding pad portion of the pellet 18, is bonded to the silver plating layer 24, which is formed only on the necessary portions of the inner lead 14. Bonding between the silver plating layer 24 and the wire 22 provides a good electrical connection. In this case, since the silver plating layer 24 is applied only to a small portion, unlike the case where the silver plating layer is applied to almost the entire surface of the inner lead 14, even if the silver plating layer 24 is slightly drooped, there is no problem. This poses no particular problem, and bondability is also very good.
一方、タブ１６には銀メツキ層が形成されてい
ないため、銀メツキ層によるマイクレーシヨンの
ポテンシヤルを減少することができ、水分による
短絡現象の発生を防止することができる。 On the other hand, since the tab 16 is not formed with a silver plating layer, the potential for microclation due to the silver plating layer can be reduced, and the occurrence of short circuit due to moisture can be prevented.
なお、リードフレームの素材が銅（Cu）系の
金属の場合には第３図に示されているように、予
め、リードフレーム上にフラツシユメツキ層２６
を、常温での酸化防止を可能にする程度の厚さに
形成しておき、そのフラツシユメツキ層２６上に
部分銀メツキ層２４を形成してもよい。 In addition, if the material of the lead frame is a copper (Cu) metal, as shown in FIG.
The partial silver plating layer 24 may be formed on the flashing layer 26 by forming the silver plating layer 26 to a thickness sufficient to prevent oxidation at room temperature.
ペレツトおよびワイヤボンデイングされたリー
ドフレームには樹脂封止パツケージ２８が、銀メ
ツキ層２４を含むインナリード１４、タブ１６、
タブ１６にボンデイングされたペレツト１８およ
びワイヤ２２を非気密封止するように成形され
る。樹脂封止パツケージ２８が成形された後、リ
ードフレームはダム１２および外枠を切り落とさ
れ、第４図に示されているようなSIP・ICが形成
される。 A resin sealing package 28 is attached to the pellet- and wire-bonded lead frame, and the inner lead 14 including the silver plating layer 24, the tab 16,
The pellet 18 and wire 22 bonded to the tab 16 are molded to form a non-hermetic seal. After the resin-sealed package 28 is molded, the dam 12 and outer frame of the lead frame are cut off to form a SIP/IC as shown in FIG.
以上本発明者によつてなされた発明を実施例に
基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しな
い範囲で種々変更可能であることはいうまでもな
い。 Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the Examples described above, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.
例えば、パツケージは樹脂封止形パツケージに
より構成するに限らず、気密封止形のセラミツク
パツケージ等により構成してもよい。 For example, the package is not limited to being a resin-sealed package, but may also be a hermetically sealed ceramic package or the like.
以上の説明では主として本発明者によつてなさ
れた発明をその背景となつた利用分野である
SIP・ICに適用した場合について説明したが、そ
れに限定されるものではなく、デユアル・イン・
ライン・パツケージを備えているIC、その他ト
ランジスタ等のような半導体装置全般に適用する
ことができる。 The above explanation mainly describes the invention made by the present inventor and the field of application that is its background.
Although we have explained the case where it is applied to SIP/IC, it is not limited to that, and it is applicable to dual-in.
It can be applied to all semiconductor devices such as ICs equipped with line packages and other transistors.
ところで、特開昭55−3641号公報には、半導体
ペレツトを接続するタブと、タブに連なり、ワイ
ヤ接続部を有するタブリードと、タブの周辺に放
射状に配置した複数のリードからなり、上記各接
続部分上に金メツキ膜を形成してなるリードフレ
ームにおいて、上記タブの半導体ペレツト接続部
とタブリードのワイヤ接続部とを、その両者間を
結ぶ直線と交差する方向でリード上に設けた非金
メツキ領域で分断したことを特徴とするリードフ
レームを用いて半導体装置を製造する技術が開示
されている。 By the way, Japanese Unexamined Patent Publication No. 55-3641 discloses a tab that connects a semiconductor pellet, a tab lead that is connected to the tab and has a wire connection part, and a plurality of leads that are arranged radially around the tab, and each of the above connections. In a lead frame in which a gold plating film is formed on the lead frame, a non-gold plated film is provided on the lead in a direction that intersects the straight line connecting the semiconductor pellet connection portion of the tab and the wire connection portion of the tab lead. A technique for manufacturing a semiconductor device using a lead frame characterized by being divided into regions has been disclosed.
しかし、この技術は、タブに形成された金メツ
キ膜とシリコンペレツトとの金・シリコン共晶層
によるボンデイングを前提とし、放熱効果の低減
をきたすことなく、金・シリコン共晶層の流れに
よるタブリードにおけるワイヤボンデイング不良
を防止することを目的とするものであつて、タブ
リードのワイヤボンデイング部とタブとを非金メ
ツキ領域によつて分断することにより、金・シリ
コン共晶層の流れを防止し、ワイヤボンデイング
不良の発生を回避するものであるから、本発明と
はその技術的思想を全く異にするものである。 However, this technology is based on the premise of bonding between the gold plating film formed on the tab and the silicon pellets using a gold/silicon eutectic layer, and the flow of the gold/silicon eutectic layer does not reduce the heat dissipation effect. The purpose is to prevent wire bonding defects in tab leads, and by separating the wire bonding part of the tab lead and the tab by a non-gold plated area, it prevents the flow of the gold/silicon eutectic layer. , the technical idea is completely different from that of the present invention since it is intended to avoid the occurrence of wire bonding defects.
以上説明したように、本発明によれば、半導体
装置に使用される貴金属である銀の使用量を大幅
に減少させることができるため、コストを著しく
低減させることができ、また、タブに銀メツキ層
が形成されないため、銀によるマイグレーシヨン
のポテンシヤル減少により、水分による短絡現象
の発生を防止することができる。
As explained above, according to the present invention, the amount of silver, which is a precious metal used in semiconductor devices, can be significantly reduced, so costs can be significantly reduced, and the tabs can be plated with silver. Since no layer is formed, the migration potential due to silver is reduced, thereby preventing the occurrence of short circuits due to moisture.
第１図は本発明の一実施例である半導体装置に
使用されているリードフレームを示す平面図、第
２図はそのペレツト取付状態を示す拡大部分断面
図、第３図は本発明の他の実施例におけるペレツ
ト取付状態を示す拡大部分断面図、第４図は本発
明の一実施例である半導体装置を示す斜視図であ
る。
１０……アウタリード、１４……インナリー
ド、１６……タブ、１８……ペレツト、２０……
タブ吊り用リード、２２……ワイヤ、２４……部
分的な銀メツキ層、２６……フラシユメツキ層、
２８……樹脂封止パツケージ。
FIG. 1 is a plan view showing a lead frame used in a semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged partial sectional view showing a state in which a pellet is attached, and FIG. FIG. 4 is an enlarged partial cross-sectional view showing a state in which pellets are attached in an embodiment, and FIG. 4 is a perspective view showing a semiconductor device according to an embodiment of the present invention. 10... Outer lead, 14... Inner lead, 16... Tab, 18... Pellet, 20...
Tab hanging lead, 22... wire, 24... partial silver plating layer, 26... flashing plating layer,
28...Resin-sealed package.
Claims (1)
部分にのみ銀メツキ層が形成されているリードフ
レームが使用されており、該リードフレームの非
銀メツキ形成層であるタブ上にペレツトがボンデ
イングされているとともに、このペレツトの電極
部に一端をボンデイングされたワイヤの他端が前
記部分銀メツキ層にボンデイングされており、こ
れらインナリード、ペレツト、タブおよびワイヤ
がパツケージにより封止されてなる半導体装置。1. A lead frame is used in which a silver plating layer is formed only in the areas necessary for wire bonding of the inner lead, and a pellet is bonded on the tab, which is a non-silver plating layer of the lead frame, and A semiconductor device in which one end of a wire is bonded to the electrode portion of the pellet and the other end is bonded to the partial silver plating layer, and these inner leads, pellets, tabs, and wires are sealed by a package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10113080A JPS5727050A (en) | 1980-07-25 | 1980-07-25 | Lead frame and semiconductor device using said lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10113080A JPS5727050A (en) | 1980-07-25 | 1980-07-25 | Lead frame and semiconductor device using said lead frame |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20117189A Division JPH0284744A (en) | 1989-08-04 | 1989-08-04 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5727050A JPS5727050A (en) | 1982-02-13 |
| JPS6342859B2 true JPS6342859B2 (en) | 1988-08-25 |
Family
ID=14292489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10113080A Granted JPS5727050A (en) | 1980-07-25 | 1980-07-25 | Lead frame and semiconductor device using said lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5727050A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS593053A (en) * | 1982-06-29 | 1984-01-09 | Sekisui Chem Co Ltd | Laminated glass |
| JPS596850U (en) * | 1982-07-06 | 1984-01-17 | 日本電気株式会社 | Lead frame for semiconductor devices |
| JPS59133049A (en) * | 1983-01-21 | 1984-07-31 | 旭硝子株式会社 | Laminated safety glass and its manufacture |
| JPS6113950U (en) * | 1984-06-29 | 1986-01-27 | 大日本印刷株式会社 | Semiconductor lead frame with metal partial coating |
| JPS6253832A (en) * | 1985-05-28 | 1987-03-09 | 旭硝子株式会社 | Laminate and manufacture thereof |
| JPH0671058B2 (en) * | 1985-06-05 | 1994-09-07 | 日立電線株式会社 | Manufacturing method of lead frame having minute spot-like plated portion |
| JPH02205062A (en) * | 1989-02-02 | 1990-08-14 | Nec Kyushu Ltd | Lead frame |
| JP2010073830A (en) * | 2008-09-17 | 2010-04-02 | Sumitomo Metal Mining Co Ltd | Lead frame and method of manufacturing same |
| CN105336839A (en) * | 2015-11-16 | 2016-02-17 | 格力电器（合肥）有限公司 | Pad, light emitting diode (LED) and pad printing template |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5278371A (en) * | 1975-12-25 | 1977-07-01 | Nec Corp | Metal ribbon for semiconductor device |
| JPS553641A (en) * | 1978-06-23 | 1980-01-11 | Hitachi Ltd | Lead frame |
| JPS554908A (en) * | 1978-06-26 | 1980-01-14 | Hitachi Ltd | Lead frame |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52129465U (en) * | 1976-03-26 | 1977-10-01 |
-
1980
- 1980-07-25 JP JP10113080A patent/JPS5727050A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5278371A (en) * | 1975-12-25 | 1977-07-01 | Nec Corp | Metal ribbon for semiconductor device |
| JPS553641A (en) * | 1978-06-23 | 1980-01-11 | Hitachi Ltd | Lead frame |
| JPS554908A (en) * | 1978-06-26 | 1980-01-14 | Hitachi Ltd | Lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5727050A (en) | 1982-02-13 |
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