JP2771475B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2771475B2
JP2771475B2 JP7133704A JP13370495A JP2771475B2 JP 2771475 B2 JP2771475 B2 JP 2771475B2 JP 7133704 A JP7133704 A JP 7133704A JP 13370495 A JP13370495 A JP 13370495A JP 2771475 B2 JP2771475 B2 JP 2771475B2
Authority
JP
Japan
Prior art keywords
resin
insulating film
semiconductor element
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7133704A
Other languages
Japanese (ja)
Other versions
JPH08330344A (en
Inventor
泰 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
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Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP7133704A priority Critical patent/JP2771475B2/en
Publication of JPH08330344A publication Critical patent/JPH08330344A/en
Application granted granted Critical
Publication of JP2771475B2 publication Critical patent/JP2771475B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
樹脂で封止される半導体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor element sealed with a resin.

【０００２】[0002]

【従来の技術】従来の樹脂封止型の半導体装置の断面を
示す図３を参照すると、アイランド３１の表面に半導体
素子３２が固着され、内部リード３０と半導体素子３２
の表面のパッドとが、金やアルミニウム等の細線２９で
電気的に接続され、これらアイランド３１，半導体素子
３２，金属細線２９，内部リード３０が樹脂２４で封止
され、樹脂２４内から外部へ外部リード３０′が導出さ
れている。2. Description of the Related Art Referring to FIG. 3, which shows a cross section of a conventional resin-encapsulated semiconductor device, a semiconductor element 32 is fixed on the surface of an island 31, and an internal lead 30 and a semiconductor element 32 are formed.
Are electrically connected to pads on the surface of the semiconductor device by thin wires 29 of gold, aluminum, or the like. These islands 31, semiconductor elements 32, thin metal wires 29, and internal leads 30 are sealed with a resin 24, and from the inside of the resin 24 to the outside. An external lead 30 'is led out.

【０００３】ここで、アイランド３１，多数の外部リー
ド３０′は、図示していないリードフレームから造られ
るもので、製造中は互いに一体となっており、後の工程
で不要部分を切断除去して、外部リード３０′が完成す
る。アイランド３１を支持していた吊りリードも切断さ
れるが、図示していない樹脂２４の表面に露出している
場合もある。Here, the island 31, and a large number of external leads 30 'are made of a lead frame (not shown), and are integrated with each other during manufacture. The external lead 30 'is completed. The suspension lead supporting the island 31 is also cut, but may be exposed on the surface of the resin 24 (not shown).

【０００４】このような樹脂封止型の半導体装置で使用
されている半導体基板の断面を示す図４を参照すると、
半導体基板２１に所望の回路機能を有する種々の半導体
領域２２が形成され、この表面に絶縁膜２３が形成さ
れ、さらにこの絶縁膜２３上に、内部の半導体領域２２
に接続された金属配線２５が形成される。FIG. 4 shows a cross section of a semiconductor substrate used in such a resin-sealed semiconductor device.
Various semiconductor regions 22 having desired circuit functions are formed on a semiconductor substrate 21, an insulating film 23 is formed on the surface thereof, and an internal semiconductor region 22 is formed on the insulating film 23.
Is formed.

【０００５】この金属配線２５は、ボンディングパッド
２７の部分を除いて、パッシベーション膜２６で覆われ
る。このような半導体基板２１は、スクライブ領域２８
で互いに切断分離されて縦横１０．０ｍｍ，厚さ０．６
ｍｍ程度の半導体チップとなり、図３の半導体素子３２
として使用される。The metal wiring 25 is covered with a passivation film 26 except for the bonding pad 27. Such a semiconductor substrate 21 has a scribe region 28.
Are cut and separated from each other by 10.0mm in height and 0.6mm in thickness.
mm, and a semiconductor chip 32 of FIG.
Used as

【０００６】近年、この種の樹脂封止された半導体装置
は、表面実装化が進み、より小型でより薄い樹脂製のパ
ッケージが要求されている。このような小型で薄いパッ
ケージへ、上述した所定寸法の半導体素子を内蔵した場
合には、従来ではなかったような新らたな問題が発生し
ている。[0006] In recent years, the surface mounting of this type of resin-sealed semiconductor device has progressed, and a smaller and thinner resin package has been demanded. When a semiconductor element having the above-mentioned predetermined size is incorporated in such a small and thin package, a new problem has occurred, which has not occurred in the related art.

【０００７】即ち、この種の半導体装置を各種機器の配
線基板に表面実装する場合、半田付けを行うが、この際
に、パッケージの樹脂と半導体素子との界面に沿って剥
離が生じることが判明した。この剥離現象は、半田付け
時の２００℃乃至３５０℃の急激な過渡期の印加熱に起
因する熱膨張差によって、樹脂と半導体素子との界面に
沿った方向のストレスが発生して起り、さらに２００℃
程度ではすでに気化状態になってしまうような残留成分
例えば水や洗浄液等が多く樹脂内に含まれている程、発
生し易くなることが判明した。また、半田付け時の印加
熱が高くなる程、発生し易いことも判明した。That is, when this type of semiconductor device is surface-mounted on a wiring board of various devices, soldering is performed. At this time, it has been found that peeling occurs along the interface between the resin of the package and the semiconductor element. did. This peeling phenomenon occurs when a stress is generated in a direction along an interface between the resin and the semiconductor element due to a difference in thermal expansion caused by an applied heat in a rapid transition period of 200 ° C. to 350 ° C. at the time of soldering. 200 ° C
It has been found that the more the residual components such as water and cleaning liquid, which are already in a vaporized state, are contained in the resin, the more easily they are generated. It has also been found that the higher the applied heat during soldering, the more easily the heat is generated.

【０００８】界面の剥離が発生すると、直ちに半導体装
置として機能に影響を及ばすことは少ないが、時間の経
過と共に次第に特性が劣化し、正常な機能をはたし得な
い程度にまで達することがある。When peeling of the interface occurs, the function of the semiconductor device is hardly affected immediately, but the characteristics gradually deteriorate with the passage of time and reach a level where normal function cannot be achieved. is there.

【０００９】このような界面の剥離が発生すると、剥離
現象は界面だけに限定されないで、薄い樹脂の時に脆弱
部分に及び、樹脂の表面にまで達し、外界の雰囲気と界
面とが連絡するようになると考えられる。これは、樹脂
の表面から、直ちに視認できないので、厄介である。従
って、このような事故が認識されないまま、大気中の水
分等が剥離部分を経て次第に浸入し、ボンディグパッド
や金属配線等に電気化学的な反応を引き起こし、腐食し
てしまう。When such interface peeling occurs, the peeling phenomenon is not limited to the interface but extends to the fragile portion when the resin is thin, reaches the surface of the resin, and communicates with the external atmosphere and the interface. It is considered to be. This is troublesome because it is not immediately visible from the surface of the resin. Therefore, without such an accident being recognized, moisture in the air and the like gradually enters through the peeled portion, causing an electrochemical reaction on the bond pad, the metal wiring, and the like, thereby causing corrosion.

【００１０】以上のような剥離現象を防止するために
は、低融点半田を用いて比較的低温で半田付けする方法
があるが、これでは半田の固着力が低下するだけでな
く、迅速に半田付け作業が行えないという欠点があり、
また樹脂封止後の樹脂中の水分量の管理を厳しく行なわ
なければならないという問題点がある。In order to prevent the above-described peeling phenomenon, there is a method of soldering at a relatively low temperature using low-melting solder. However, this method not only reduces the fixing force of the solder but also quickly solders the solder. There is a disadvantage that you can not do the attaching work,
There is also a problem that the amount of water in the resin after resin sealing must be strictly controlled.

【００１１】樹脂で封止した半導体装置の樹脂クラック
発生数を減少させることを目的とした特開平３−２２４
６５号公報を参照すると、半導体素子の表面及びアイラ
ンドの裏面に、ポリイミド系樹脂被膜を形成することに
より、応力の集中を防止する技術が記載されている。Japanese Patent Application Laid-Open No. 3-224 aims to reduce the number of occurrences of resin cracks in a semiconductor device sealed with resin.
With reference to Japanese Patent Application Publication No. 65-65, there is described a technique for preventing concentration of stress by forming a polyimide resin film on the front surface of a semiconductor element and the back surface of an island.

【００１２】しかしながら、このような技術では、ポリ
イミド系樹脂を被膜する工程が追加されるだけでなく、
放熱効果が低下してしまい、しかもアイランドの裏面に
まで被膜しないと効果がない等の問題がある。However, such a technique not only adds a step of coating the polyimide resin, but also
There is a problem in that the heat radiation effect is reduced, and there is no effect unless the back surface of the island is coated.

【００１３】また、半導体素子とボンディングワイヤと
が接触しないように、この基板の端部に絶縁膜を形成す
る技術が特開平３−２３３９４５号公報に見られるが、
これはワイヤの電気的接触事故を防止する効果があるだ
けで、このような絶縁膜では界面剥離減少を防止する効
果がないことも判明した。Japanese Patent Application Laid-Open No. 3-233945 discloses a technique for forming an insulating film on the edge of the substrate so that the semiconductor element does not come into contact with the bonding wire.
It has been found that this has only the effect of preventing the electrical contact accident of the wire, and that such an insulating film does not have the effect of preventing the interface peeling reduction.

【００１４】[0014]

【発明が解決しようとする課題】以上のような諸問題点
に鑑み、本発明では、次の各課題を掲げる。 （１）パッケージの樹脂と半導体素子との界面に剥離が
生じないようにすること。 （２）半田付け時の温度を厳しく管理する必要性がな
く、急激に温度を上昇させてもよいようにすること。 （３）特に樹脂と半導体素子との界面に沿った方向のス
トレスに耐えるようにすること。 （４）大気中に含まれる水分等に影響を受けないように
すること。 （５）半導体装置としての特性が劣化しないようにする
こと。 （７）外部リードの半田付け作業が迅速に行えるように
すること。 （８）樹脂被膜工程を追加しないで済むようにするこ
と。In view of the above problems, the present invention has the following problems. (1) To prevent separation at the interface between the resin of the package and the semiconductor element. (2) There is no need to strictly control the temperature during soldering, and the temperature may be rapidly increased. (3) To withstand stress particularly in the direction along the interface between the resin and the semiconductor element. (4) Avoid being affected by moisture contained in the atmosphere. (5) To prevent the characteristics of the semiconductor device from deteriorating. (7) Soldering work of external leads can be performed quickly. (8) It is not necessary to add a resin coating step.

【００１５】[0015]

【課題を解決するための手段】本発明の構成は、半導体
素子の主表面のボンディングパッドと内部リードとが金
属細線で電気的に接続され、樹脂で封止してなる半導体
装置において、前記ボンディングパッドと前記半導体素
子の主表面の周端部の間に、所定の厚さと幅の帯状の凸
部を、前記半導体素子の主表面の絶縁膜の平均的厚さよ
りも１μｍ以上厚く形成していることを特徴とする。Configuration of the present invention According to an aspect of the bonding pads and inner leads of the main surface of the semiconductor element is electrically connected by metal wires, the semiconductor device obtained by encapsulating in a resin, the bonding Between the pad and the peripheral end of the main surface of the semiconductor element, a band-shaped convex part having a predetermined thickness and width is formed according to the average thickness of the insulating film on the main surface of the semiconductor element.
It is characterized in that it is formed thicker than 1 μm .

【００１６】特に前記凸部が、絶縁性の膜とこの表面に
形成したパッシベーション膜とからなることを特徴とす
る。In particular, the projection is characterized by comprising an insulating film and a passivation film formed on the surface thereof.

【００１７】さらに前記凸部が、前記半導体素子の側面
から内方に所定の寸法入ったところの表面上に形成され
ていることを特徴とする。Further, the semiconductor device is characterized in that the convex portion is formed on a surface having a predetermined size inward from a side surface of the semiconductor element.

【００１８】[0018]

【実施例】本発明の一実施例を図１，図２を参照して説
明する。この実施例の半導体基板１は、第２の絶縁膜４
をスクライブ領域８の近傍に形成してなる凸部１５以外
は、図３，図４に示した従来技術と共通するため、共通
した構成については説明を省略する。 An example of the embodiment of the present invention FIG. 1, theory with reference to FIG. 2
I will tell . The semiconductor substrate 1 of this embodiment has a second insulating film 4
3 and 4 are common to the prior art shown in FIGS. 3 and 4 except for the convex portion 15 formed near the scribe region 8, and the description of the common configuration will be omitted.

【００１９】この凸部１５は、絶縁性の膜とこの表面を
覆うパッシべーション膜とからなり、半導体基板１のス
クライブ領域８即ち後で半導体素子１３となる領域の端
部から所定の寸法入ったところの表面上に形成されてい
る。凸部１５の断面は方形であるが、半導体基板の主表
面上のうち前記後で半導体素子１３となる各領域の周端
部に沿って帯状を呈する。即ち、半導体基板の主表面上
から見ると、方形の帯状をなす。[0019] The convex portion 15 is composed of a passivation film covering the surface with an insulating film, the edge of the region to be the scribe region 8 i.e. later semiconductor element 13 of the semiconductor substrate 1
It is formed on the surface at a predetermined dimension from the part . Although the cross section of the convex portion 15 is rectangular, it has a band shape along the peripheral end portion of each region on the main surface of the semiconductor substrate, which will be the semiconductor element 13 later . That is, when viewed from the main surface of the semiconductor substrate, the semiconductor substrate has a rectangular band shape.

【００２０】第１の絶縁膜３の表面に、第２の絶縁膜４
と金属配線５とが形成される。第２の絶縁膜４は、スク
ライブ領域８から１００μｍ乃至２００μｍ程度内側の
第１の絶縁膜３上に、１μｍ乃至１０μｍ程度の厚さと
幅とで形成される。図示はしないが、この第２の絶縁膜
４は、方形の前記後で半導体素子１３となる各領域の表
面に全周に渡り形成される。この第２の絶縁膜４の内側
面は、金属配線５の側面に接し、外側は第１の絶縁膜３
が表面にあり、スクライブ領域８に達する。On the surface of the first insulating film 3, a second insulating film 4
And metal wiring 5 are formed. The second insulating film 4 is formed with a thickness and a width of about 1 μm to 10 μm on the first insulating film 3 about 100 μm to 200 μm inside the scribe region 8. Although not shown, the second insulating film 4 is formed over the entire surface of each of the rectangular regions which will be the semiconductor element 13 later . The inner surface of the second insulating film 4 is in contact with the side surface of the metal wiring 5 and the outer surface is the first insulating film 3.
On the surface and reaches the scribe area 8.

【００２１】第２の絶縁膜４の表面、及び第２の絶縁膜
４とスクライブ領域８との間の第１の絶縁膜３の表面，
ボンディングパッド７の部分を除く金属配線５の表面
を、パッシベーション膜６で覆って、保護する。公知の
ＣＶＤ及びフォトリソグラフィ技術で造ることのできる
第２の絶縁膜４は、ポリイミド樹脂，プラズマＣＶＤＳ
ｉＮ膜，プラズマＣＶＤＳｉＯＮ膜，またはＣＶＤＳｉ
Ｏ2 膜で形成される。The surface of the second insulating film 4 and the surface of the first insulating film 3 between the second insulating film 4 and the scribe region 8;
The surface of the metal wiring 5 excluding the bonding pad 7 is covered with a passivation film 6 for protection. The second insulating film 4 which can be formed by known CVD and photolithography techniques is made of polyimide resin, plasma CVDS
iN film, plasma CVD SiON film, or CVDSi
It is formed of an O 2 film.

【００２２】以上のように形成された半導体基板１は、
スクライブ領域８で切断分離されて、図２に示す半導体
素子１３として、アイランド１１の表面に固着される。
次に、ボンディングパッド７と内部リード１０とに、２
０乃至３０μｍ程度の金又はアルミニウムの金属細線９
が、熱圧着又は超音波熱圧着法にて、ボンディングされ
る。The semiconductor substrate 1 formed as described above
The semiconductor element 13 is cut and separated at the scribe region 8 and fixed to the surface of the island 11 as the semiconductor element 13 shown in FIG.
Next, the bonding pad 7 and the internal lead 10
Gold or aluminum thin metal wire 9 of about 0 to 30 μm
Are bonded by thermocompression bonding or ultrasonic thermocompression bonding.

【００２３】その後、あらかじめ加熱されて流動化した
熱硬化性の樹脂材料を、封止用金型に注入して成形す
る。注入される際、樹脂材料は半導体素子の表面に一様
に、付着し、第２の絶縁膜４によって形成された凸部１
５の表面にも隈なく付着し、この凸部１５はあたかもく
さび状に樹脂１２内に嵌入したような状態となってお
り、後工程の半田付けで発生する特に横方向１４のスト
レスによる剥離を防止する。Thereafter, the thermosetting resin material that has been heated and fluidized in advance is injected into a molding die and molded. When the resin material is injected, the resin material uniformly adheres to the surface of the semiconductor element, and the convex portion 1 formed by the second insulating film 4 is formed.
5, and the projections 15 are in a state of being fitted into the resin 12 in a wedge-like manner. To prevent.

【００２４】即ち、外部リードと配線基板との接続時に
印加される２００℃から３５０℃程度の急激な熱に起因
する封止樹脂１２と半導体素子１との界面の横方向１４
のすべりを抑えることができる。このため、封止樹脂１
２の表面に達するまでの剥離乃至亀裂の発生がなく、従
って大気中の水分等が侵入して、腐食事故等が生じる心
配がなくなる。That is, the lateral direction 14 of the interface between the sealing resin 12 and the semiconductor element 1 caused by the rapid heat of about 200 ° C. to 350 ° C. applied when the external lead is connected to the wiring board.
Slip can be suppressed. Therefore, the sealing resin 1
No peeling or cracking occurs up to the surface of No. 2; therefore, there is no fear that moisture or the like in the atmosphere may enter and cause a corrosion accident or the like.

【００２５】ここで、用いる封止樹脂１２は、特に性状
に限定されることがなく、例えばエポキシ樹脂が用いら
れ、この他に硬化剤、硬化促進剤等が含まれていてもよ
い。Here, the properties of the sealing resin 12 to be used are not particularly limited. For example, an epoxy resin is used, and in addition, a curing agent, a curing accelerator and the like may be contained.

【００２６】この実施例の絶縁膜４の厚さ（高さ）は、
半導体基板１の主表面の平均的厚さよりも、少なくとも
１．０μｍ以上好ましくは２．０μｍ以上厚くなってい
る必要がある。さらに、絶縁膜４の幅は、厚さと略等し
いことが好ましい。The thickness (height) of the insulating film 4 in this embodiment is:
It must be at least 1.0 μm or more, preferably 2.0 μm or more thicker than the average thickness of the main surface of the semiconductor substrate 1. Further, the width of the insulating film 4 is preferably substantially equal to the thickness.

【００２７】尚、この実施例によれば、内部リード１０
とパッド７との離間距離が３乃至５ｍｍと長い場合に金
属細線９がたわみ、半導体素子１３に接触するようなこ
とがあっても、第２の絶縁膜４で形成された凸部１５に
当接するため、なんら支障がない。また、アイランド１
１に半導体素子１３を固着する際に、マウントソルダー
が側面からはい上る心配があるが、この凸部１５により
阻止することができる。さらに、半導体素子１３が不良
品と判定された際に、そのマークとしてインクを摘下又
は塗布するが、このインクが半導体素子１３の表面から
流出するのを、凸部１５が阻止する働きもある。According to this embodiment, the internal leads 10
When the distance between the pad and the pad 7 is as long as 3 to 5 mm, even if the thin metal wire 9 bends and comes into contact with the semiconductor element 13, even if the thin metal wire 9 comes into contact with the semiconductor element 13, the thin metal wire 9 contacts the convex portion 15 formed by the second insulating film 4. There is no problem to touch. Island 1
When the semiconductor element 13 is fixed to the semiconductor device 1, there is a concern that the mount solder may go up from the side surface. Further, when the semiconductor element 13 is determined to be defective, the ink is picked up or applied as a mark, and the protrusion 15 also functions to prevent the ink from flowing out of the surface of the semiconductor element 13. .

【００２８】また、この実施例では、封止樹脂１２が唯
一つの材料で済むから、二種類の封止樹脂を用いる場合
に比較して、注入工程等が著しく簡単で済むという利点
もある。Further, in this embodiment, since only one material is used for the sealing resin 12, there is an advantage that the injection step and the like can be remarkably simplified as compared with the case where two kinds of sealing resins are used.

【００２９】この実施例では、表面実装化された小型，
薄型のフラットパッケージに限定されるものではなく、
この他にＳＯＰ（Ｓｍａｌｌ Ｏｕｔ−ｌｉｎｅ Ｐａ
ｃｋａｇｅ）、ＳＯＪ（Ｓｍａｌｌ Ｏｕｔ−ｌｉｎｅ
Ｊ−ｌｅａｄ）や、ＰＬＣＣ（Ｐｌａｓｔｉｃ Ｌｅ
ａｄｅｄ Ｃｈｉｐ Ｃａｒｒｉｅｒ）等にも適用でき
る。In this embodiment, a small, surface-mounted
It is not limited to thin flat packages,
In addition, SOP (Small Out-line Pa)
cage), SOJ (Small Out-line)
J-lead), PLCC (Plastic Le)
Also, the present invention can be applied to an added chip carrier.

【００３０】[0030]

【発明の効果】以上説明した通り、本発明は、スクライ
ブ領域から所定寸法だけ内方の半導体素子表面に、凸部
を形成したことにより、上述した（１）乃至（８）の各
課題がことごとく達成され、半導体装置を実装する際の
半田付け温度及び樹脂封止後の樹脂中の水分の影響を受
けることがなくなるため、半田付け温度及び樹脂の水分
量の管理が不用となり、さらに信頼度の高い半導体装置
が得られるという効果が得られる。As described above, according to the present invention, each of the above-mentioned problems (1) to (8) can be solved by forming a convex portion on the surface of the semiconductor element which is inside the scribe region by a predetermined dimension. It is not affected by the soldering temperature when mounting the semiconductor device and the moisture in the resin after resin encapsulation, so the management of the soldering temperature and the amount of moisture in the resin becomes unnecessary, and the reliability is further improved. The effect of obtaining a high semiconductor device can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例の半導体基板を示す断面図で
ある。FIG. 1 is a sectional view showing a semiconductor substrate according to one embodiment of the present invention.

【図２】一実施例の半導体基板から得られた半導体素子
の封止状態を示す断面図である。FIG. 2 is a cross-sectional view showing a sealed state of a semiconductor element obtained from a semiconductor substrate according to one embodiment.

【図３】従来の樹脂封止半導体装置を示す断面図であ
る。FIG. 3 is a sectional view showing a conventional resin-sealed semiconductor device.

【図４】従来の樹脂封止対象となる半導体基板を示す断
面図である。FIG. 4 is a cross-sectional view showing a conventional semiconductor substrate to be sealed with a resin.

【符号の説明】[Explanation of symbols]

１，２１ 半導体基板 ２，２２ 半導体領域 ３ 第１の絶縁膜 ４ 第２の絶縁膜 ５，２５ 金属配線 ６，２６ パッシベーション膜 ７，２７ ボンディングパッド ８，２８ スクライブ領域 ９，２９ 金属細線 １０，３０ 内部リード １０′，３０′ 外部リード １１，３１ アイランド １２，２４ 封止樹脂 １３，３２ 半導体素子 １４ 横方向 １５ 凸部 ２３ 絶縁膜 1, 21 semiconductor substrate 2, 22 semiconductor region 3 first insulating film 4 second insulating film 5, 25 metal wiring 6, 26 passivation film 7, 27 bonding pad 8, 28 scribe region 9, 29 thin metal wire 10, 30 Internal lead 10 ', 30' External lead 11, 31 Island 12, 24 Sealing resin 13, 32 Semiconductor element 14 Lateral direction 15 Convex part 23 Insulating film

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体素子の主表面のボンディングパッ
ドと内部リードとが金属細線で電気的に接続され、樹脂
で封止してなる半導体装置において、前記ボンディング
パッドと前記半導体素子の主表面の周端部の間に、所定
の厚さと幅の帯状の凸部を、前記半導体措置の主表面の
絶縁膜の平均的厚さよりも１μｍ以上厚く形成し、前記
凸部が、絶縁性の膜とこの表面に形成したパッシベーシ
ョン膜とからなることを特徴とする半導体装置。In a semiconductor device in which a bonding pad on a main surface of a semiconductor element and an internal lead are electrically connected by a thin metal wire and sealed with a resin, the bonding pad and a periphery of the main surface of the semiconductor element are provided. Between end portions, a band-shaped convex portion having a predetermined thickness and width is formed to be 1 μm or more thicker than the average thickness of the insulating film on the main surface of the semiconductor device ,
The protruding part is the insulating film and the passive base formed on this surface.
A semiconductor device, comprising a semiconductor film .
JP7133704A 1995-05-31 1995-05-31 Semiconductor device Expired - Lifetime JP2771475B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7133704A JP2771475B2 (en) 1995-05-31 1995-05-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7133704A JP2771475B2 (en) 1995-05-31 1995-05-31 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH08330344A JPH08330344A (en) 1996-12-13
JP2771475B2 true JP2771475B2 (en) 1998-07-02

Family

ID=15110947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7133704A Expired - Lifetime JP2771475B2 (en) 1995-05-31 1995-05-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2771475B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022835U (en) * 1988-06-20 1990-01-10
JPH02166743A (en) * 1988-12-21 1990-06-27 Nec Corp Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPH08330344A (en) 1996-12-13

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