JPS63262857A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法

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Publication number
JPS63262857A
JPS63262857A JP62098014A JP9801487A JPS63262857A JP S63262857 A JPS63262857 A JP S63262857A JP 62098014 A JP62098014 A JP 62098014A JP 9801487 A JP9801487 A JP 9801487A JP S63262857 A JPS63262857 A JP S63262857A
Authority
JP
Japan
Prior art keywords
wiring
chip
silicon substrate
substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62098014A
Other languages
English (en)
Other versions
JPH0834264B2 (ja
Inventor
Katsunori Nishiguchi
勝規 西口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP62098014A priority Critical patent/JPH0834264B2/ja
Priority to KR1019880004395A priority patent/KR920003595B1/ko
Priority to CA000564487A priority patent/CA1275331C/en
Priority to EP88106396A priority patent/EP0288052A3/en
Publication of JPS63262857A publication Critical patent/JPS63262857A/ja
Priority to US07/649,183 priority patent/US5188984A/en
Publication of JPH0834264B2 publication Critical patent/JPH0834264B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （産業上の利用分野〕 本発明はガリウムヒ素等の如く、高速かつ高集積度の化
合物半導体素子を用いる半導体装置に関し、特に高速度
の信号処理に用いられるものである。また、本発明はこ
のような半導体装置の製造方法に関する。
〔従来の技術〕
高周波帯域、特にＧＨ２帯での高速信号処理に適した半
導体装置として、ガリウムヒ素を用いる半導体装置が多
用されている。
このようなガリウムヒ素半導体装置にあける従来の実装
形態の例を第２図に示す。
第２図（ａ＞は従来のガリウムヒ素半導体装置の一例の
構成を示す断面図である。図示の通り、セラミックス製
のベース１の中央部に形成された凹部２にはガリウムヒ
素チップ３が載置され、このガリウムヒ素チップ３上の
電極（図示せず。）とベース１の凹部２の周囲に形成さ
れた厚膜印刷配線４とは、金等のボンディングワイヤ５
により接続されている。
ところが、セラミックスの表面は凹凸が多く、高精度の
配線は困難で必るため、厚膜印刷配線４は例えば最小幅
１００μｍ程度であり、高密度の実装は不可能でおる。
特に、グランド配線の形成が困難であることからインピ
ーダンス整合を行なえず、配線パターンの自由度が少な
い。
第２図（ｂ）は他の実装形態を示す断面図である。図示
の通り、平坦なセラミックス製のベース１１の上面には
薄膜配線１２が形成され、中央部に載置されダイボンデ
ィングされたガリウムヒ素チップ１３との間でワイヤ１
４により接続がなされている。この場合にも、セラミッ
クスを用いているため、薄膜配線であっても最小幅１０
μｍ程度の配線が可能であるに過ぎず、多面配線も不可
能であるので高密度実装には適していない。
第２図（Ｃ）は更に他の従来の実装形態を示す断面図で
ある。図示の通りこの場合には、表面に薄膜配線層２２
を形成したシリコン基板２１上の中央部にガリウムヒ素
チップ２３がダイボンディングされ、これと薄膜配線層
２２との間でワイヤ２４により接続がなされている。こ
の場合には、シリコン基板を採用したことにより表面の
平坦度が大幅に改善されるため、最小幅３μｍ程度の薄
膜配線層の形成が可能である。
〔発明が解決しようとする問題点〕
しかしながら、これらのいずれの場合にもワイヤを使用
しているため、そのための制約を受け、十分な高密度化
は達成されていない。また、ワイヤは配線容量等を伴う
ため、遅延を招きやすく高速動作には適さない。
そこで本発明は、十分な高密度化を達成でき、しかも高
速動作特性にすぐれた半導体装置およびその製造方法を
提供することを目的とする。
〔問題点を解決するための手段〕
本発明に係る半導体装置は、表面に第１の配線を形成し
てあるシリコン基板に設けられた凹部に化合物半導体チ
ップが埋め込まれ、チップとシリコン基板の凹部との間
の空隙上に平坦化手段が形成され、この上に化合物半導
体チップ上の電極と第１の配線とを接続する第２の配線
とを備えたことを特徴とする。
また、本発明に係る半導体装置の製造方法は、エッチス
トッパとなるイオンを注入したシリコン基板の所定領域
を、エッチストッパが存在する部分までエツチングして
凹部を形成し、この凹部に化合物半導体チップを収納し
、凹部の周囲壁と化合物半導体チップの側壁間の空隙部
を覆うように絶縁膜を形成してパターニングし、このパ
ターニングされた樹脂膜の上に化合物半導体チップの電
極とシリコン基板にあらかじめ形成された第１の配線層
とを接続するよう、第２の配線層を形成したことを特徴
とする特 〔作用〕 本発明に係る半導体装置は、以上のように構成されるの
で、ワイヤを使用することなく薄膜で精密な配線が行わ
れるため、より高密度の配線が可能となり、配線容量の
低下等から高速動作が可能となるように作用する。
また、本発明に係る半導体装置の製造方法は、エッチス
トッパを打ち込んでから凹部形成のためのエツチングを
行い、また基板凹部と化合物半導体チップ間の空隙部を
覆うように絶縁膜を形成し、その上に配線層を形成する
ようにしているので、ワイヤボンディング工程を用いる
ことなく上記半導体装置を確実に製造することができる
。
〔実施例〕
以下、添附図面を参照して、本発明の一実施例を説明す
る。なお、図面の説明において同一の要素には同一の符
号を付し、重複する説明を省略する。
第１図は実施例に係る半導体装置と、その製造方法を示
す工程別断面図である。
第１図（ｅ）はダイシング後のチップ５０を示しており
、シリコン基板５１の表面下に凹部５４が形成され、こ
こにガリウムヒ素チップ５５が埋め込まれている。そし
て、チップ５５の表面はシリコン基板５１の表面と同一
面をなすようになっている。また、このガリウムヒ素チ
ップの表面と凹部５４の周囲の基板５１の表面との間に
は、互いの端部にまたがるように絶縁膜５６が形成され
ている。また、この絶縁膜５６の上には例えばアルミニ
ウムの配線層５７が形成され、従来の半導体装置のよう
にワイヤボンディングによる配線は存在していない。
この結果、ワイヤボンディングのためのボンティングパ
ッド等が不要となるので、そのためのスペースが不要で
あり、その分だけ多く薄膜配線を形成でき、高密度配線
が可能となっている。また、ワイヤの容量やインダクタ
ンスに起因する高周波特性の低下を防止できるようにな
っている。
次に、このような半導体装置の製造工程を説明する。
まず、結晶方位（１００）面の表面に所定のパターンで
配線（図示せず）が形成されているシリコン基板５０を
準備する。なお、このシリコン基板５０の所定の深さの
領域には、ホウ素イオンを７ｘ　１０１９／ｃｍ３の高
ドーズ量となるようにあらかじめ打ち込んで形成したエ
ッチストッパ層５２が存在している（第１図（ａ）に図
示）。次に、シリコン基板５１の上に例えば二酸化シリ
コン（Ｓｉｎ２）、窒化シリコン（Ｓｒ　Ｎ）等からな
るマスク５３をパターニングして形成し、エチレンジア
ミン、ピロカテコール、水の混合液によるエッチャント
を用いて異方性エツチングを行う。
このようにすると、水平面に対して５４．７°の角度を
なす結晶方位（１１１）の側壁５４ａを有する凹部５４
が形成される（第１図（ｂ）に図示）。この凹部５４の
深さは約２００μｍである。
次に、マスク５３を除去し、既に回路パターンが形成さ
れた厚さ２００μｍのガリウムヒ素チップ５５を凹部５
４の中に載置し、例えば金−錫共晶合金を用いてダイボ
ンディングする（第１図（Ｃ）に図示）。このようにす
ると、ガリウムヒ素チップ５５の厚ざと凹部５４の深さ
が等しいため、ガリウムヒ素チップ５５の表面とシリコ
ン基板５１の表面とは同一面をなす。
続いて、仝而にポリイミド等の絶縁膜５６をコーティン
グし、ガリウムヒ素チップ５５上の１ｔｆＡおよび基板
５１の表面上の配線が露出するようパターニングを行う
（第１図（ｄ）に図示）。なお、この実施例の場合には
、絶縁膜のコーティングの際に凹部側壁５４ａとガリウ
ムヒ素チップ５５の側壁との間の空隙は、通常は完全に
は埋められていないが、空隙は微小であるのでこれで十
分である。しかし、この空隙を完全に埋めるようにして
もよい。
次に、例えばアルミニウムのスパッタリング等により全
面に配線層を形成し、これをパターニングすることによ
り、ガリウムヒ素チップ５５上の電極および基板５１の
表面上の配線を接続する上層配線層５７を形成する。こ
の配線の幅は１０μｍ程度であり、一般の薄膜配線より
も太いが、ワイヤのような変形は無いため、従来と比べ
てより高密度の配線が可能となる。
最侵に、全体の上にシリコン窒化膜やシリコン酸化膜等
の絶縁膜（図示せず。）をプラズマＣＶＤ法やＥＣＲス
パッタリング法により堆積して保護膜とし、ダイシング
装置のベース（図示せず。）に粘着チー１５８を用いて
固着する。そして、ダイシングブレードによりダイシン
グを行って個々のチップ５０に分割する（第１図（ｅ）
に図示）。このようにして得られたチップは、例えば錫
−銀共晶合金を用いてパッケージのベースにグイボンデ
ィングされ、パッケージが形成される。
本発明は上記実施例に限定されるものではなく、種々の
変形が可能である。
例えば、凹部形成のためのエツチングとしてエチレンジ
アミン系のエッチャントを用いているが、ヒドラジン系
のエッチセントでもよい。そして、このエッチャントの
種類に応じてマスクの材料を変更すればよい。
また、平坦化を行う層としてはポリイミド層に限ること
なく、耐熱性と絶縁性にすぐれた材料であればいかなる
ものでも使用することができる。
また、配線層の材料もアルミニウムに限られるものでは
なく、種々の導電材料を用いることができる。
ざらに、シリコン板の表面を結晶方位（１１０）面とす
れば、９０度の側壁の孔部をエツチングにより形成する
ことができる。
〔発明の効果〕
以上、詳細に説明した通り、本発明に係る半導体装置に
よれば、シリコン基板に形成された四部中に化合物半導
体チップが載置され、薄膜配線で化合物半導体チップと
シリコン基板上の配線が接続されているので、ワイヤボ
ンディングにおいて避けられない配線容量に伴う信号遅
延を防止することができるとともに、配線領域を拡大す
ることができるという効果がある。
また、本発明に係る半導体装置の製造方法によれば、ワ
イヤボンディングが不要であるので、工程の短縮化を図
ることができるという効果がある。
【図面の簡単な説明】
第１図は本発明に係る半導体装置およびその製造方法を
示す工程別素子断面図、第２図は従来のガリウムヒ素半
導体装置の構成を示す素子断面図である。 １．１１・・・セラミック基板、２１．５１・・・シリ
コン基板、３，１３，２３．５５・・・ガリウムヒ素チ
ップ、５２・・・エッチストッパ層、５３・・・マスク
、５４・・・凹部、５６・・・絶縁膜、５７・・・上層
配線層。 特許出願人　　住友電気工業株式会社 代理人弁理士　　　長谷用　　芳　　樹第　　１　　図

Claims (1)

  1. 【特許請求の範囲】 １、表面に第１の配線を形成してあるシリコン基板に設
    けられた凹部に埋め込まれた化合物半導体チップと、 この化合物半導体チップと前記シリコン基板の凹部との
    間の空隙上に形成された平坦化手段と、この平坦化手段
    の上に形成され、前記化合物半導体チップ上の電極と前
    記シリコン基板上の第１の配線とを接続する第２の配線
    と を備える半導体装置。 ２、前記化合物半導体チップの表面と前記シリコン基板
    の表面とが、ほぼ同一平面をなすことを特徴とする特許
    請求の範囲第１項記載の半導体装置。 ３、前記平坦化手段が、コーティングされたポリイミド
    膜である特許請求の範囲第１項または第２項のいずれか
    に記載の半導体装置。 ４、前記化合物半導体がガリウムヒ素である特許請求の
    範囲第１項ないし第３項のいずれかに記載の半導体装置
    。 ５、エッチストッパとなるイオンを所定の深さの領域に
    注入したシリコン基板の所定領域を、前記エッチストッ
    パが存在する部分までエッチングして凹部を形成する工
    程と、 前記凹部に化合物半導体チップを収納する工程と、 前記凹部の周囲の壁と前記化合物半導体チップの側壁の
    間の空隙部を覆うように絶縁膜を形成してパターニング
    する工程と、 このパターニングされた絶縁膜の上に前記化合物半導体
    チップの電極と前記シリコン基板上にあらかじめ形成さ
    れた第１の配線層とを接続するように第２の配線層を形
    成する工程と を備える半導体装置の製造方法。 ６、前記絶縁膜がポリイミドである特許請求の範囲第５
    項記載の半導体装置の製造方法。７、前記凹部を形成す
    るためのエッチングがエチレンジアミン系のエッチャン
    トを用いるものである特許請求の範囲第５項記載の半導
    体装置の製造方法。
JP62098014A 1987-04-21 1987-04-21 半導体装置およびその製造方法 Expired - Fee Related JPH0834264B2 (ja)

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JP62098014A JPH0834264B2 (ja) 1987-04-21 1987-04-21 半導体装置およびその製造方法
KR1019880004395A KR920003595B1 (ko) 1987-04-21 1988-04-18 반도체장치 및 그 제조방법
CA000564487A CA1275331C (en) 1987-04-21 1988-04-19 Recessed semiconductor device
EP88106396A EP0288052A3 (en) 1987-04-21 1988-04-21 Semiconductor device comprising a substrate, and production method thereof
US07/649,183 US5188984A (en) 1987-04-21 1991-02-04 Semiconductor device and production method thereof

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JP62098014A JPH0834264B2 (ja) 1987-04-21 1987-04-21 半導体装置およびその製造方法

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JPS63262857A true JPS63262857A (ja) 1988-10-31
JPH0834264B2 JPH0834264B2 (ja) 1996-03-29

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JP2012004314A (ja) * 2010-06-16 2012-01-05 Mems Core Co Ltd 実装体及びその製造方法

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KR920003595B1 (ko) 1992-05-04
EP0288052A2 (en) 1988-10-26
US5188984A (en) 1993-02-23
CA1275331C (en) 1990-10-16
JPH0834264B2 (ja) 1996-03-29
KR880013254A (ko) 1988-11-30
EP0288052A3 (en) 1989-08-23

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