JPS63254788A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPS63254788A JPS63254788A JP8952087A JP8952087A JPS63254788A JP S63254788 A JPS63254788 A JP S63254788A JP 8952087 A JP8952087 A JP 8952087A JP 8952087 A JP8952087 A JP 8952087A JP S63254788 A JPS63254788 A JP S63254788A
- Authority
- JP
- Japan
- Prior art keywords
- board
- printed wiring
- wiring board
- printed
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 20
- 239000004020 conductor Substances 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000003973 paint Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000011253 protective coating Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 241000531908 Aramides Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明はエレクトロニクス用電子機器に用いるプリント
配線板に関し、とりわけ半導体チップを実装した構造に
関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a printed wiring board used in electronic equipment, and more particularly to a structure in which semiconductor chips are mounted.
従来の技術
半導体チップを、プリント配線板に直接実装する方法と
してフィルムキャリヤ、チップオンボードなどの技術が
すでに存在する。前者は複雑な工程とコスト高のため一
般的な技術として用いられていない。基材であるポリイ
ミドフィルムのフレキシブル性はユーザにとって必ずし
も便利ではなく、またそのコスト高も普及を妨げる原因
となっている。後者はガラス布エポキシ板のような一般
的なボードに展開しセラミックベースの印刷配線板に取
って代りつつあるが、チップの特性検査をおこないに<
<、半導体チップ搭載数の検査歩留まり低下によるコス
ト高を招来している。2. Description of the Related Art Techniques such as film carrier and chip-on-board techniques already exist as methods for directly mounting semiconductor chips on printed wiring boards. The former method is not commonly used because of its complicated process and high cost. The flexibility of polyimide film, which is the base material, is not necessarily convenient for users, and its high cost also hinders its widespread use. Although the latter has been developed into common boards such as glass cloth epoxy boards and is replacing ceramic-based printed wiring boards, it is still difficult to test chip characteristics.
<This has led to higher costs due to lower inspection yields for the number of semiconductor chips mounted.
発明が解決しようとする問題点
半導体チップのプリント配線板への装着を低いコストと
、検査可能の形で実証しなければならない。Problem to be Solved by the Invention It is necessary to demonstrate the mounting of semiconductor chips on printed wiring boards at low cost and in a testable manner.
問題点を解決するための手段
本発明は、半導体チップを子プリント板の小片上に、ダ
イ及びワイアによるボンディングを行ない、エポキシ樹
脂の滴下とCスティンへの硬化をおこない、保護コート
樹脂を形成し半導体チップ取付側を孔に向けて親プリン
ト板の孔に蓋をする形で搭載する。半導体チップ及びそ
のワイアボンディング部の総合高さは親プリント板の孔
の深さ内に位置させる。Means for Solving the Problems The present invention involves bonding a semiconductor chip onto a small piece of a child printed board using a die and wire, and then dripping epoxy resin and curing it to the C stain to form a protective coating resin. Mount the semiconductor chip with the mounting side facing the hole and cover the hole in the parent printed circuit board. The overall height of the semiconductor chip and its wire bonding portion is located within the depth of the hole in the parent printed circuit board.
作用
本発明によるとプリント配線板の表層配線と、半導体チ
ップ搭載の子プリント板の表層の銅導体とは、面対面接
続ではんだによって接合される。According to the present invention, the surface wiring of a printed wiring board and the surface copper conductor of a sub-printed board on which a semiconductor chip is mounted are joined by solder in a surface-to-surface connection.
すなわち、他のチップ部品の電極と同様に又同時にはん
だペースト印刷法によるリフロウソルダリングが可能で
ある。また両面配線チップキャリヤとすれば、チップ搭
載を両面におこなう事も、又、配線及び他の微少部品の
取り付はスペースとしても利用できる。In other words, it is possible to perform reflow soldering using the solder paste printing method in the same way and simultaneously with the electrodes of other chip components. Furthermore, if a double-sided wiring chip carrier is used, chips can be mounted on both sides, and the space can be used for mounting wiring and other minute parts.
実施例
図示のように、半導体チップ4として、1.2X1.6
mm、ワイア結線用の電極接続用端子14のものを子プ
リント板1として、厚さ0.2mmのアーラミドせんい
にエポキシ樹脂を含浸させたものに厚さ0.017mの
銅箔3を接着させた円形のプリント配線板の直径15I
IIl!1に装着する。はんだ付けのできる銅箔−樹脂
ペイント、めっき銅配線を用いることは当然可能である
。アウターワイアボンド部は銅箔3の一部にあらかじめ
金、銀。As illustrated in the embodiment, the semiconductor chip 4 is 1.2×1.6
mm, electrode connection terminal 14 for wire connection was used as child printed board 1, and 0.017 m thick copper foil 3 was adhered to 0.2 mm thick Aramide fiber impregnated with epoxy resin. Circular printed wiring board diameter 15I
IIl! Attach it to 1. It is of course possible to use solderable copper foil-resin paint or plated copper wiring. For the outer wire bond part, a part of the copper foil 3 is coated with gold and silver in advance.
ニッケル等で1〜10μの厚さのめっきをおこなう。ボ
ンディングワイア5の接続点の配置ピッチは0.2+a
mとした。ダイボンディングは無溶剤銀ペイントで16
0℃、30分の硬化をおこなう。Plating with nickel or the like to a thickness of 1 to 10 μm is performed. The arrangement pitch of the connection points of the bonding wires 5 is 0.2+a
It was set as m. Die bonding is done with solvent-free silver paint 16
Curing was performed at 0°C for 30 minutes.
その後、エポキシ樹脂ペイントのドリッピングを直径9
wmとして行い、保護コート樹脂9の形成をおこなう。Then apply the epoxy resin paint dripping to a diameter of 9 mm.
wm to form the protective coating resin 9.
この半球の最大高さは約1.5mmとする。The maximum height of this hemisphere is approximately 1.5 mm.
親プリント板2の開孔部7の直径は約10mmとする。The diameter of the opening 7 in the parent printed board 2 is approximately 10 mm.
半導体チップ面を下にして載置する。親プリント板2上
に用意した対向電極3には、他のチップ部品と同様には
んだペースト(錫/鉛63/37 )6の印刷がおこな
われており、215℃で15秒〜20秒の条件ではんだ
接合が、他のコンデンサ抵抗器等のチップ部品10の電
極11と共に接続する。親プリント板2としてアクセス
ホールのあるもの又、同じ孔に半導体チップを搭載した
子プリント板を親プリント板の両面に搭載する事も板厚
によっては可能である。Place the semiconductor chip face down. The counter electrode 3 prepared on the main printed board 2 is printed with solder paste (tin/lead 63/37) 6 like other chip components, and is heated at 215°C for 15 to 20 seconds. Solder joints connect together with electrodes 11 of chip components 10 such as other capacitor resistors. Depending on the board thickness, it is also possible to use a parent printed board 2 with an access hole, or to mount child printed boards with semiconductor chips mounted in the same holes on both sides of the parent printed board.
発明の効果
半導体チップを載置する子プリント板が、親プリント板
から分離独立した形で用いられ、ボンディング用のめっ
き、ボッティング樹脂のドリッピングと加熱硬化の処理
はすでになされているので親プリント板に対する加工を
要しないのでコストメリットがある。半導体のチップキ
ャリヤの下面を面対面で、他のチップ部品と同時にリフ
ロウソルダリングをおこないつる。その時半導体搭載部
分は孔内部にあるため、リフロウソルダによる過熱、汚
染等の影響を受けることがなくなり、信頼性が向上する
。半導体チップを下面に搭載した場合、上面を他の配線
、ターミナルに用い、段ちがいの配線板へのりフロラソ
ルダリングをおこなう事ができる。また子基板が金属基
板であれば金属板を放熱体として用いる事もできる。Effects of the invention The child printed board on which the semiconductor chip is placed is used separately from the parent printed board, and the plating for bonding, dripping and heat curing of the botting resin have already been done, so the parent print There is a cost advantage since no processing is required for the plate. Reflow soldering is performed on the underside of a semiconductor chip carrier face-to-face at the same time as other chip components. At this time, since the semiconductor mounting portion is inside the hole, it is not affected by overheating, contamination, etc. due to reflow solder, and reliability is improved. When a semiconductor chip is mounted on the bottom surface, the top surface can be used for other wiring and terminals, and floral soldering can be performed on wiring boards in different stages. Furthermore, if the slave board is a metal board, the metal plate can also be used as a heat sink.
図面は本発明実施例の断面図である。
1・・・・・・子プリント板、2・・・・−・親プリン
ト板、3・・・・・・銅導体、4・・・・・・半導体チ
ップ、5・・・・・・ボンディングワイア、6・・・・
・・はんだ、7・・・・・・親プリント板の孔、8・・
・・・・親プリント板の銅箔、9・・・・・・半導体チ
ップを搭載した子プリント板、10・・・・・・チップ
部品、11・・・・・・チップ部品の電極。The drawings are cross-sectional views of embodiments of the present invention. 1... Child printed board, 2... Main printed board, 3... Copper conductor, 4... Semiconductor chip, 5... Bonding Wire, 6...
...Solder, 7...Hole in main printed board, 8...
. . . Copper foil of main printed board, 9 . . . Child printed board with semiconductor chip mounted, 10 . . . Chip components, 11 . . . Electrodes of chip components.
Claims (1)
装した子プリント板1とを組み合わせた実装構造であっ
て、子プリント板に実装した半導体チップの厚さと、半
導体へのボンディングワイア5の占める部分の余裕との
総和が親プリント板2の厚さをこえない範囲で配置され
、かつ載置部は表面に突出し、その電極接続部が親プリ
ント板の表層導体に接続されている構造のプリント配線
板。This is a mounting structure in which a child printed circuit board 1 is mounted with a semiconductor chip 4 mounted in a hole of a parent printed wiring board, and the thickness of the semiconductor chip mounted on the child printed wiring board and the portion occupied by bonding wires 5 to the semiconductor are A printed wiring board having a structure in which the total thickness of the printed wiring board 2 including the allowance does not exceed the thickness of the main printed board 2, the mounting part protrudes from the surface, and the electrode connection part is connected to the surface conductor of the main printed board. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8952087A JPS63254788A (en) | 1987-04-10 | 1987-04-10 | Printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8952087A JPS63254788A (en) | 1987-04-10 | 1987-04-10 | Printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63254788A true JPS63254788A (en) | 1988-10-21 |
Family
ID=13973075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8952087A Pending JPS63254788A (en) | 1987-04-10 | 1987-04-10 | Printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63254788A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009037833A1 (en) * | 2007-09-21 | 2009-03-26 | Panasonic Corporation | Solid printed wiring board, method for manufacturing solid printed wiring board, and electronic component module |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49119159A (en) * | 1973-03-20 | 1974-11-14 |
-
1987
- 1987-04-10 JP JP8952087A patent/JPS63254788A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49119159A (en) * | 1973-03-20 | 1974-11-14 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009037833A1 (en) * | 2007-09-21 | 2009-03-26 | Panasonic Corporation | Solid printed wiring board, method for manufacturing solid printed wiring board, and electronic component module |
JPWO2009037833A1 (en) * | 2007-09-21 | 2011-01-06 | パナソニック株式会社 | Three-dimensional printed wiring board, method for manufacturing the same, and electronic component module |
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