JPS6325404B2 - - Google Patents
Info
- Publication number
- JPS6325404B2 JPS6325404B2 JP1032779A JP1032779A JPS6325404B2 JP S6325404 B2 JPS6325404 B2 JP S6325404B2 JP 1032779 A JP1032779 A JP 1032779A JP 1032779 A JP1032779 A JP 1032779A JP S6325404 B2 JPS6325404 B2 JP S6325404B2
- Authority
- JP
- Japan
- Prior art keywords
- head
- erase
- circuit
- drive circuit
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B19/00—Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head
- G11B19/02—Control of operating function, e.g. switching from recording to reproducing
- G11B19/04—Arrangements for preventing, inhibiting, or warning against double recording on the same blank or against other recording or reproducing malfunctions
Landscapes
- Digital Magnetic Recording (AREA)
Description
【発明の詳細な説明】
本発明はフロツピーデイスク装置等におけるヘ
ツド切換方式の改良に係わり、特に書込終了時か
ら消去終了までのロスタイムをなくそうとするも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a head switching system in a floppy disk device, etc., and is particularly intended to eliminate loss time from the end of writing to the end of erasing.
磁気デイスク装置においては、通常複数の書込
み、読出し用の磁気ヘツドを有している。しか
し、フロツピーデイスク装置では従来は１つの磁
気ヘツドしか有していないが、最近の記録容量の
増加、技術の発展に伴つて、２つの磁気ヘツドを
有するものが作られるようになつた。この場合の
ヘツド切換方式は従来第１図に示すように構成さ
れている。 A magnetic disk device usually has a plurality of magnetic heads for writing and reading. However, floppy disk devices have conventionally had only one magnetic head, but with recent increases in recording capacity and technological developments, devices having two magnetic heads have come to be manufactured. The head switching system in this case has conventionally been constructed as shown in FIG.
図中１は磁気媒体上にデータを書込む書込駆動
回路、２，３は磁気ヘツド選択駆動回路、４は消
去回路、５，６は書込み、読出し用磁気ヘツド、
７，８はトンネルイレーズを行なう消去ヘツドで
ある。 In the figure, 1 is a write drive circuit for writing data on a magnetic medium, 2 and 3 are magnetic head selection drive circuits, 4 is an erase circuit, 5 and 6 are magnetic heads for writing and reading,
7 and 8 are erase heads that perform tunnel erase.
このように構成されたヘツド切換回路では次の
ような欠点が生じる。磁気ヘツドにトンネルイレ
ーズ方式を採用しているので、書込ヘツドのON
状態と消去ヘツドのON状態とでは第２図に示す
ように、時間的にずれている。特に書込終了から
消去の終了までの時間が問題となる。この間はヘ
ツド切換禁止期間なので、CPU側からはこの間
のヘツド切換を行なつてはならない。すなわち、
CPUは書込みが終了してから消去が終了するま
での期間は他へのアクセスはできない。この期間
はフロツピーデイスク装置などでは数百Msecに
も及ぶので長いロスタイムである。 The head switching circuit constructed in this manner has the following drawbacks. The magnetic head uses a tunnel erase method, so when the write head is turned on,
As shown in FIG. 2, there is a time lag between this state and the ON state of the erase head. In particular, the time from the end of writing to the end of erasing is a problem. Since this is a head switching prohibition period, the CPU must not switch heads during this period. That is,
The CPU cannot access anything else during the period from the end of writing to the end of erasing. This period extends to several hundred Msec in a floppy disk device, so it is a long loss time.
本発明はこのような従来例のロスタイムをなく
そうとするものである。 The present invention aims to eliminate such loss time of the conventional example.
以下本発明の詳細をその一実施例を示す第３図
によつて説明すると、１１は書込ヘツドの駆動回
路、１２は消去駆動回路を動作させるタイミング
ゼネレータ、１３は消去ヘツドに電流を流す消去
駆動回路、１４はオア回路、１５はヘツド選択信
号を記憶するラツチ回路、１６，１７はヘツド選
択用の駆動回路、１８，１９は書込み、読出し用
ヘツド、２０，２１は消去用ヘツドである。 The details of the present invention will be explained below with reference to FIG. 3 showing one embodiment thereof. Reference numeral 11 is a write head drive circuit, 12 is a timing generator that operates the erase drive circuit, and 13 is an erase head that supplies current to the erase head. 14 is an OR circuit, 15 is a latch circuit for storing a head selection signal, 16 and 17 are drive circuits for head selection, 18 and 19 are write and read heads, and 20 and 21 are erase heads.
このように構成されたヘツド切換回路の動作を
第４図を参照して説明する。まず、書込可能信号
ｂが出ると、オア回路１４の出力が“１”となつ
てｄのようになり、ラツチ回路１５によつてヘツ
ド選択信号がラツチされる。これは書込時のヘツ
ド切換を防止するためである。書込が終了した後
に、消去を完全するために、一定時間消去動作信
号ｃが出る。この消去動作信号がオア回路１４の
もう１つの入力として入つているので、消去が終
了するまでヘツド選択信号はラツチ回路１５によ
つてラツチされたままである。そして消去が終了
した時点でラツチ回路１５は解放される。 The operation of the head switching circuit constructed in this way will be explained with reference to FIG. First, when the write enable signal b is output, the output of the OR circuit 14 becomes "1" as shown in d, and the latch circuit 15 latches the head selection signal. This is to prevent head switching during writing. After the write is completed, the erase operation signal c is output for a certain period of time to complete the erase. Since this erase operation signal is input as another input to the OR circuit 14, the head selection signal remains latched by the latch circuit 15 until the erase is completed. The latch circuit 15 is released when erasing is completed.
従つて書込が終了した時点でCPUは他へのア
クセスが可能となり、従来例によるロスタイムを
なくすことが可能となる。 Therefore, once the writing is completed, the CPU can access other parts, making it possible to eliminate the loss time caused by the conventional example.
第１図は従来のヘツド切換回路のブロツク図で
第２図はその動作のタイミング図、第３図は本発
明を実施するヘツド切換回路のブロツク図で第４
図はその各部信号のタイミング図である。
１１…書込ヘツド駆動回路、１２…タイミング
ゼネレータ、１３…消去ヘツド駆動回路、１４…
オア回路、１５…ラツチ回路、１６，１７…ヘツ
ド選択用駆動回路、１８，１９…書込ヘツド、２
０，２１…消去ヘツド。
FIG. 1 is a block diagram of a conventional head switching circuit, FIG. 2 is a timing diagram of its operation, and FIG. 3 is a block diagram of a head switching circuit implementing the present invention.
The figure is a timing diagram of each part of the signal. DESCRIPTION OF SYMBOLS 11...Write head drive circuit, 12...Timing generator, 13...Erase head drive circuit, 14...
OR circuit, 15... Latch circuit, 16, 17... Head selection drive circuit, 18, 19... Write head, 2
0, 21...Erase head.
Claims (1)
して消去ヘツド駆動回路を動作させるタイミング
ゼネレータと、ヘツド選択駆動回路を制御するヘ
ツド選択信号を記憶するラツチ回路と、上記書込
可能信号と上記ゼネレータよりの消去動作信号と
のオアによつて上記ラツチ回路を制御するオア回
路とを具備し、消去が終了するまで上記ヘツド選
択信号がラツチされるようにすることを特徴とす
るヘツド切換方式。1 a timing generator that operates an erase head drive circuit in conjunction with a write enable signal to the write head drive circuit; a latch circuit that stores a head selection signal that controls the head selection drive circuit; and a latch circuit that stores a head selection signal that controls the head selection drive circuit; A head switching system comprising: an OR circuit for controlling the latch circuit by ORing with the erase operation signal from the generator, and the head selection signal is latched until the erase is completed. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1032779A JPS55105810A (en) | 1979-02-02 | 1979-02-02 | Head switching system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1032779A JPS55105810A (en) | 1979-02-02 | 1979-02-02 | Head switching system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55105810A JPS55105810A (en) | 1980-08-13 |
| JPS6325404B2 true JPS6325404B2 (en) | 1988-05-25 |
Family
ID=11747112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1032779A Granted JPS55105810A (en) | 1979-02-02 | 1979-02-02 | Head switching system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55105810A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0731775B2 (en) * | 1985-05-14 | 1995-04-10 | 株式会社日立製作所 | Magnetic recording / reproducing device |
| JPS6275903A (en) * | 1985-09-27 | 1987-04-07 | Canon Electronics Inc | Magnetic disk recording device |
| JPH0778847B2 (en) * | 1986-02-28 | 1995-08-23 | ティアツク株式会社 | Double-sided magnetic disk device |
-
1979
- 1979-02-02 JP JP1032779A patent/JPS55105810A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55105810A (en) | 1980-08-13 |
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