JPS63193553A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS63193553A JPS63193553A JP63007389A JP738988A JPS63193553A JP S63193553 A JPS63193553 A JP S63193553A JP 63007389 A JP63007389 A JP 63007389A JP 738988 A JP738988 A JP 738988A JP S63193553 A JPS63193553 A JP S63193553A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- semiconductor device
- substrate
- conductors
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 239000004020 conductor Substances 0.000 claims description 61
- 239000000758 substrate Substances 0.000 claims description 15
- 239000003989 dielectric material Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 description 2
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 description 1
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
【発明の詳細な説明】
〔産業上の利用分野]
本発明は、絶縁基板と、この絶縁基板上に配置されて電
気的に互いに分離された少なくとも2つの導体路と、接
触を有する少なくとも1つの半導体基体と、前記接触と
導体路との間を接続する電気的接続部と、それぞれ1つ
が前記両導体路の1つに電気的に接続された接続導体と
を備えた半導体装置に関する。
気的に互いに分離された少なくとも2つの導体路と、接
触を有する少なくとも1つの半導体基体と、前記接触と
導体路との間を接続する電気的接続部と、それぞれ1つ
が前記両導体路の1つに電気的に接続された接続導体と
を備えた半導体装置に関する。
この種の半導体装置は本件出願人により既に特願昭62
−263642号にて提案されている。
−263642号にて提案されている。
この既提案の実施例においては、負荷電流を案内する接
続導体は基板の互いに対向する端部に配置されている。
続導体は基板の互いに対向する端部に配置されている。
従って、接続導体は負荷回路内に比較的高いインダクタ
ンスを形成し、そのために2、勾配の負荷電流でもって
半導体装置をターンオフする際、半導体デバイスを破壊
させるような高電圧が誘起される。
ンスを形成し、そのために2、勾配の負荷電流でもって
半導体装置をターンオフする際、半導体デバイスを破壊
させるような高電圧が誘起される。
本発明は、主電流回路のインダクタンスを減少させるこ
とを目的とする。
とを目的とする。
(課題を解決するための手段〕
この目的を達成するために、本発明は、接続導体は接近
して一緒にかつ少なくとも一部分が互いに平行に配置さ
れることを特徴とする。
して一緒にかつ少なくとも一部分が互いに平行に配置さ
れることを特徴とする。
本発明の実施態様は特許請求の範囲第2項以下に記載さ
れている。
れている。
〔実施例]
次に、本発明を図面に示された実施例に基づいて詳細に
説明する。
説明する。
第1図は本発明の第1実施例を示す斜視図、第2図は本
発明の第2実施例を示す平面図である。
発明の第2実施例を示す平面図である。
第1図に示された半導体装置は基板1上に構成されてい
る。基板は良絶縁性で熱良導性の材料、例えば酸化アル
ミニウムまたは酸化ベリリウムから成る。基板上には導
体路2,3.4および5が設けられている。導体路2.
3はU字形に形成されており、導体路2内に導体路3が
入れられている。導体路3上には半導体基体6が設けら
れ、導体路と電気的に接続されている。この半導体基体
は例えばパワーMO5FETまたはバイポーラトランジ
スタである。この場合には、半導体基体はMOS F
ETであるとする。半導体基体6は導体路3とは反対側
の面にゲート接触7およびソース接触8を有している。
る。基板は良絶縁性で熱良導性の材料、例えば酸化アル
ミニウムまたは酸化ベリリウムから成る。基板上には導
体路2,3.4および5が設けられている。導体路2.
3はU字形に形成されており、導体路2内に導体路3が
入れられている。導体路3上には半導体基体6が設けら
れ、導体路と電気的に接続されている。この半導体基体
は例えばパワーMO5FETまたはバイポーラトランジ
スタである。この場合には、半導体基体はMOS F
ETであるとする。半導体基体6は導体路3とは反対側
の面にゲート接触7およびソース接触8を有している。
ドレイン接触は下面に位置して、導体路3に接続されて
いる。ゲート接触7はボンディングワイヤ13を介して
導体路4に接続されている。ソース接触8はボンディン
グワイヤ9を介して導体路2に接続されている。さらに
、ソース接触8はボンディングワイヤ10を介して第4
の導体路5に接続されている。
いる。ゲート接触7はボンディングワイヤ13を介して
導体路4に接続されている。ソース接触8はボンディン
グワイヤ9を介して導体路2に接続されている。さらに
、ソース接触8はボンディングワイヤ10を介して第4
の導体路5に接続されている。
導体路2.3は負荷回路内のインダクタンスを出来る限
り僅かにするという理由から接近して一緒に配置されて
いる。しかしながら、それらの間隔は必要な絶縁耐力が
保証されるような大きさである。さらに、導体路2.3
は互いに平行に位置している0両U字形導体路2.3の
同様に互いに平行に位置する横桁上には、それぞれ1つ
の接続導体11.12が設けられている、例えばろう付
けされている。接Vt導体11.12は外部導線への接
続に供される接続面14.15に到るまで互いに平行で
ある。それらの間隔aは両導体路2゜3間の間隔と同様
に、絶縁耐力が保証される範囲で出来る限り小さく選定
されている。
り僅かにするという理由から接近して一緒に配置されて
いる。しかしながら、それらの間隔は必要な絶縁耐力が
保証されるような大きさである。さらに、導体路2.3
は互いに平行に位置している0両U字形導体路2.3の
同様に互いに平行に位置する横桁上には、それぞれ1つ
の接続導体11.12が設けられている、例えばろう付
けされている。接Vt導体11.12は外部導線への接
続に供される接続面14.15に到るまで互いに平行で
ある。それらの間隔aは両導体路2゜3間の間隔と同様
に、絶縁耐力が保証される範囲で出来る限り小さく選定
されている。
上述した構成によれば、主電流回路のインダクタンスは
冒頭で述べた既提案の半導体装置に比較して約半分とな
る。従って、ii流をターンオフする際に発生する誘導
電圧も同様に半分になる。
冒頭で述べた既提案の半導体装置に比較して約半分とな
る。従って、ii流をターンオフする際に発生する誘導
電圧も同様に半分になる。
導体路4および導体路5はゲート端子17およびソース
補助端子16にそれぞれ接続されている。
補助端子16にそれぞれ接続されている。
MOSFETは端子16.17間に印加された電圧によ
って制御される。制御回路は従って誘導的には充分に負
荷回路から減結合されており、それゆえ負荷電流の増大
は半導体装置のターンオン特性に僅かしか影響しない。
って制御される。制御回路は従って誘導的には充分に負
荷回路から減結合されており、それゆえ負荷電流の増大
は半導体装置のターンオン特性に僅かしか影響しない。
接続導体11.12間の間隔aが僅かであるにも拘わら
ず存在するインダクタンスは、接続導体間の中間空間に
、比誘電率が1よりも大きい誘電体を充填することによ
って部分的に補償することができる。この場合、コンデ
ンサとして使用可能な材料を使用することができる。誘
電体に加えて、または、誘電体に代えて、両接続導体間
には絶縁シートを配置することができる。
ず存在するインダクタンスは、接続導体間の中間空間に
、比誘電率が1よりも大きい誘電体を充填することによ
って部分的に補償することができる。この場合、コンデ
ンサとして使用可能な材料を使用することができる。誘
電体に加えて、または、誘電体に代えて、両接続導体間
には絶縁シートを配置することができる。
インダクタンスを僅かにするという理由から、接続導体
は出来る限り短くすることが推奨される。
は出来る限り短くすることが推奨される。
従って、接続導体は基板1の表面に対して特に垂直に設
けられる。
けられる。
半導体装置が複数の半導体基体を有する場合には、第2
図に示されるように、接続導体11.12は基板1およ
び導体路2.3上に対称に配置される。第2図に示され
た実施例においては、導体路2.3はそれぞれ対称軸線
22に対して鏡面対称に形成された閉リングを構成して
いる。同様に、半導体基体6は導体路3上に対称軸線2
2に対して対称に分散されている。接続導体11.12
は対称軸線の両側に配置されている。短絡を回避するた
めに、接続導体11は脚部18.19を有し、接続導体
12は脚部20.21を存している。半導体基体6はゲ
ート接触7およびソース接触8が同様に対称軸線22に
対して対称となるように導体路3上に配置されている。
図に示されるように、接続導体11.12は基板1およ
び導体路2.3上に対称に配置される。第2図に示され
た実施例においては、導体路2.3はそれぞれ対称軸線
22に対して鏡面対称に形成された閉リングを構成して
いる。同様に、半導体基体6は導体路3上に対称軸線2
2に対して対称に分散されている。接続導体11.12
は対称軸線の両側に配置されている。短絡を回避するた
めに、接続導体11は脚部18.19を有し、接続導体
12は脚部20.21を存している。半導体基体6はゲ
ート接触7およびソース接触8が同様に対称軸線22に
対して対称となるように導体路3上に配置されている。
第1図は本発明の第1の実施例を示す斜視図、第2図は
本発明の第2の実施例を示す平面図であ1・・・基板、
2〜5・・・導体路、6・・・半導体基体、7・・・ゲ
ート接触、8・・・ソース接触、9,10.13・・・
ボンディングワイヤ、11.12・・・接続導体、14
.15・・・接続面、16・・・ソース補助端子、17
・・・ゲート端子、18〜21・・・脚部、22・・・
対称軸線。 8118)代理人弁珪士冨村 謬)7::7:どr′5
1玉: 0[?艮τ士
本発明の第2の実施例を示す平面図であ1・・・基板、
2〜5・・・導体路、6・・・半導体基体、7・・・ゲ
ート接触、8・・・ソース接触、9,10.13・・・
ボンディングワイヤ、11.12・・・接続導体、14
.15・・・接続面、16・・・ソース補助端子、17
・・・ゲート端子、18〜21・・・脚部、22・・・
対称軸線。 8118)代理人弁珪士冨村 謬)7::7:どr′5
1玉: 0[?艮τ士
Claims (1)
- 【特許請求の範囲】 1)絶縁基板と、この絶縁基板上に配置されて電気的に
互いに分離された少なくとも2つの導体路と、接触を有
する少なくとも1つの半導体基体と、前記接触と導体路
との間を接続する電気的接続部と、それぞれ1つが前記
両導体路の1つに電気的に接続された接続導体とを備え
た半導体装置において、前記接続導体(11,12)は
接近して一緒にかつ少なくとも一部分が互いに平行に配
置されることを特徴とする半導体装置。 2)両導体路(2,3)は基板(1)の同一表面上に配
置され、前記両導体路は互いに平行に位置し、接続導体
は前記導体路の互いに隣接して平行に位置する部分に固
定され、前記接続導体は基板表面上に直角に立設される
ことを特徴とする特許請求の範囲第1項記載の半導体装
置。 3)第1導体路(2)と第2導体路(3)とはそれぞれ
鏡面対称に形成され、半導体基体(6)は前記第2導体
路(3)上に対称に分散して配置され、接続導体(11
,12)は対称軸線(22)の両側で対応する導体路に
接続されることを特徴とする特許請求の範囲第1項また
は第2項記載の半導体装置。 4)両接続導体間の空間には、比誘電率が1よりも大き
い誘電体が充填されることを特徴とする特許請求の範囲
第1項ないし第3項のいずれか1項に記載の半導体装置
。 5)両接続導体(11,12)間には絶縁シートが配置
されることを特徴とする特許請求の範囲第4項記載の半
導体装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE3701650.4 | 1987-01-21 | ||
DE3701650 | 1987-01-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63193553A true JPS63193553A (ja) | 1988-08-10 |
JPH0680762B2 JPH0680762B2 (ja) | 1994-10-12 |
Family
ID=6319219
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63007389A Expired - Lifetime JPH0680762B2 (ja) | 1987-01-21 | 1988-01-14 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4907068A (ja) |
EP (1) | EP0277546B1 (ja) |
JP (1) | JPH0680762B2 (ja) |
DE (1) | DE3871968D1 (ja) |
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JP6838243B2 (ja) | 2017-09-29 | 2021-03-03 | 日立Astemo株式会社 | 電力変換装置 |
Citations (5)
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JPS5797661A (en) * | 1980-12-10 | 1982-06-17 | Mitsubishi Electric Corp | Semiconductor device |
JPS5816632A (ja) * | 1981-07-24 | 1983-01-31 | Q P Corp | 容器入り殺菌マツシユポテトの製造方法 |
JPS59177951A (ja) * | 1983-03-29 | 1984-10-08 | Toshiba Corp | 半導体装置 |
JPS6393126A (ja) * | 1986-10-08 | 1988-04-23 | Fuji Electric Co Ltd | 半導体装置 |
JPS6390850U (ja) * | 1986-12-04 | 1988-06-13 |
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US4213141A (en) * | 1978-05-12 | 1980-07-15 | Solid State Scientific Inc. | Hybrid transistor |
US4237522A (en) * | 1979-06-29 | 1980-12-02 | International Business Machines Corporation | Chip package with high capacitance, stacked vlsi/power sheets extending through slots in substrate |
US4328530A (en) * | 1980-06-30 | 1982-05-04 | International Business Machines Corporation | Multiple layer, ceramic carrier for high switching speed VLSI chips |
JPS58181968A (ja) * | 1982-04-16 | 1983-10-24 | 国産金属工業株式会社 | ドア錠のハンドル装置 |
JPS60239051A (ja) * | 1984-05-11 | 1985-11-27 | Mitsubishi Electric Corp | 半導体装置 |
DE3538933A1 (de) * | 1985-11-02 | 1987-05-14 | Bbc Brown Boveri & Cie | Leistungshalbleitermodul |
-
1987
- 1987-12-24 US US07/137,607 patent/US4907068A/en not_active Expired - Lifetime
-
1988
- 1988-01-14 JP JP63007389A patent/JPH0680762B2/ja not_active Expired - Lifetime
- 1988-01-20 EP EP88100792A patent/EP0277546B1/de not_active Expired - Lifetime
- 1988-01-20 DE DE8888100792T patent/DE3871968D1/de not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5797661A (en) * | 1980-12-10 | 1982-06-17 | Mitsubishi Electric Corp | Semiconductor device |
JPS5816632A (ja) * | 1981-07-24 | 1983-01-31 | Q P Corp | 容器入り殺菌マツシユポテトの製造方法 |
JPS59177951A (ja) * | 1983-03-29 | 1984-10-08 | Toshiba Corp | 半導体装置 |
JPS6393126A (ja) * | 1986-10-08 | 1988-04-23 | Fuji Electric Co Ltd | 半導体装置 |
JPS6390850U (ja) * | 1986-12-04 | 1988-06-13 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5185097A (en) * | 1989-12-29 | 1993-02-09 | Canon Kabushiki Kaisha | Polymeric liquid-crystalline compound, liquid-crystal composition containing it, and liquid-crystal drive |
JPH03292764A (ja) * | 1990-04-11 | 1991-12-24 | Okuma Mach Works Ltd | インバータモジュール |
JPH06291251A (ja) * | 1993-04-06 | 1994-10-18 | Sansha Electric Mfg Co Ltd | 電力用半導体モジュール |
JP2003046058A (ja) * | 2001-07-30 | 2003-02-14 | Mitsubishi Electric Corp | 半導体装置 |
JP4601874B2 (ja) * | 2001-07-30 | 2010-12-22 | 三菱電機株式会社 | 半導体装置 |
JP2005347561A (ja) * | 2004-06-03 | 2005-12-15 | Toshiba Corp | パワー半導体モジュールおよび電力変換装置 |
JP2014011227A (ja) * | 2012-06-28 | 2014-01-20 | Sumitomo Electric Ind Ltd | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
EP0277546A1 (de) | 1988-08-10 |
DE3871968D1 (de) | 1992-07-23 |
JPH0680762B2 (ja) | 1994-10-12 |
US4907068A (en) | 1990-03-06 |
EP0277546B1 (de) | 1992-06-17 |
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