JPS6314507A - Limiter amplifier circuit - Google Patents
Limiter amplifier circuitInfo
- Publication number
- JPS6314507A JPS6314507A JP61160062A JP16006286A JPS6314507A JP S6314507 A JPS6314507 A JP S6314507A JP 61160062 A JP61160062 A JP 61160062A JP 16006286 A JP16006286 A JP 16006286A JP S6314507 A JPS6314507 A JP S6314507A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- dynamic range
- power supply
- amplifier circuit
- limiter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007423 decrease Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 4
- 230000003321 amplification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 101150030723 RIR2 gene Proteins 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は増幅器が多段に直列接続されたリミット増幅回
路において、電源における雑音に対して影響を少なくし
たＤ リミッタ増幅回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a D limiter amplifier circuit in which amplifiers are connected in series in multiple stages, and which reduces the influence of noise in a power supply.
第２図を参照して従来のリミッタ増幅回路を説明する。 A conventional limiter amplifier circuit will be explained with reference to FIG.
入力端子ＩＮは増幅器１の入力に接続され、前記増幅器
１の出力は次段の増幅器２の入力端子に接続され前記増
幅器２の出力は、次段の増幅器の入力端子に接続されさ
らにｎ段目の増幅器に接続される。一方前記増幅記１，
２及びｎの最高電位及び最低電位部は共通の正電源Ｖｃ
ｅ韮びに負電源ＶＩＥにそれぞれ接続され、リミッタ増
幅回路を構成している。The input terminal IN is connected to the input of an amplifier 1, the output of the amplifier 1 is connected to the input terminal of the next stage amplifier 2, the output of the amplifier 2 is connected to the input terminal of the next stage amplifier, and the output of the amplifier 1 is connected to the input terminal of the next stage amplifier. connected to the amplifier. On the other hand, the amplification 1,
The highest potential and lowest potential parts of 2 and n are connected to a common positive power supply Vc.
It is connected to the negative power supply VIE and the negative power supply VIE, respectively, and constitutes a limiter amplifier circuit.
かかる従来のリミッタ回路において、増幅器１の入力に
極小電気信号（正弦波等）が入力した場合増幅器を多段
に接続する事によって利得を大きくとる事ができ、最終
段の増幅器ｎの出力端子ＯＵＴからは十分増幅された出
力信号（矩形波）を得る事ができる。In such a conventional limiter circuit, when an extremely small electric signal (such as a sine wave) is input to the input of the amplifier 1, the gain can be increased by connecting the amplifiers in multiple stages, and the gain can be increased from the output terminal OUT of the final stage amplifier n. can obtain a sufficiently amplified output signal (square wave).
しかしながら多段に接続されたリミッタ増幅回路のダイ
ナミックレンジは正電源Ｖｃｃ及び負電源ＶＩＥで定ま
るので入力信号が非常に小さく、初段の増幅器の利得を
太きクシ、前記増幅器のダイナミックレンジを広くしよ
うとした時、前記正電源ｖＣＣ及び負電源ＶＥＲに雑音
が生じた場合、前記雑音は前記増幅器によって増幅され
、入力信号と雑音の区別がつかなくなシミ源に対する雑
音による影響を前記増幅器は受け、リミッタ増幅回路の
特性を劣化させるという欠点があった。However, the dynamic range of a limiter amplifier circuit connected in multiple stages is determined by the positive power supply Vcc and the negative power supply VIE, so the input signal is very small, so it was attempted to increase the gain of the first stage amplifier to widen the dynamic range of the amplifier. When noise occurs in the positive power supply vCC and the negative power supply VER, the noise is amplified by the amplifier, making it impossible to distinguish between the input signal and the noise, and the amplifier is affected by the noise on the stain source. This has the disadvantage of deteriorating the circuit characteristics.
本発明は上記従来のものの欠点を除去すべくなされたも
のであり、その目的のするところは前記リミッタ増幅器
の電源に対する雑音の影響を抑制し、回路の特性を向上
させたリミッタ増幅回路を提供する事にある。前記目的
を達成するために本発明によるリミッタ増幅回路は増幅
器が少なくとも２段以上直列に接続されたシリミッタ増
幅回路に２いて前記増幅器の最高電位部及び最低電位部
にそれぞれ抵抗器Ｒ１’＆介して正電源Ｖｃｃ及び負電
源ＶＥＥに接続され、さらに前記増幅器に接続された次
段の増幅器の最高電位部及び最低電位部それぞれ抵抗器
Ｒ２を介して前記正電源Ｖｃｃ及び負電源ＶＥＲに接続
され、さらに前記増幅器にｎ段目に接続された増幅器の
最高電位部及び最低電位部にそれぞれ抵抗器Ｒｎｉ介し
て前記正電源Ｖｃｃ及び負電源ＶＥＥＩ／ｉ１″筬続さ
れ、前記抵抗器ＲＩＲ２及びＲｎの抵抗値はそれぞれＲ
１＞Ｒ２＞・・・）Ｒｎである事を特徴とするリミッタ
増幅回路を提供する事にある。The present invention has been made to eliminate the drawbacks of the conventional circuits described above, and its purpose is to provide a limiter amplifier circuit that suppresses the influence of noise on the power supply of the limiter amplifier and improves the characteristics of the circuit. It's true. In order to achieve the above object, the limiter amplifier circuit according to the present invention includes a limiter amplifier circuit in which at least two stages of amplifiers are connected in series, and a resistor R1' and a resistor connected to the highest potential part and the lowest potential part of the amplifier, respectively. connected to the positive power supply Vcc and the negative power supply VEE, and further connected to the positive power supply Vcc and the negative power supply VER via resistors R2, respectively, to the highest potential part and the lowest potential part of the next-stage amplifier connected to the amplifier; The positive power supply Vcc and the negative power supply VEEI/i1'' are connected to the highest potential part and the lowest potential part of the amplifier connected to the nth stage of the amplifier through resistors Rni, respectively, and the resistance values of the resistors RIR2 and Rn are each R
An object of the present invention is to provide a limiter amplifier circuit characterized in that Rn (1>R2>...).
次に本発明にリミッタ増幅回路において実施例を挙ぎ図
面を参照して説明する。Next, an embodiment of the present invention in a limiter amplifier circuit will be described with reference to the drawings.
第１図は本発明による実施例の回路でｓｂ第２図と同一
部分は同一符号で示しその説明は省略する。FIG. 1 shows a circuit according to an embodiment of the present invention, and the same parts as those in FIG.
第１図においてＷＪｌの増幅器１の最高電位部及び最低
電位部にそれぞれ抵抗器Ｒ１を介して正電源Ｖｃｃ及び
負電源Ｖｇｚに接続され前記第１の増幅器１の出力が第
２の増幅器２０入力に接続され、前記増幅器２の最高電
位部及び最低電位部にそれぞれ抵抗器Ｒ２を介して前記
正電源Ｖｃｃ及び負電源に接続され、又、前記第２の増
幅器２の出力は次段の増幅器に接続され、さらにｎ段目
に接続され、さらにｎ段目に接続された第ｎの増幅器ｎ
。In FIG. 1, the highest potential part and the lowest potential part of the amplifier 1 of WJl are connected to the positive power supply Vcc and the negative power supply Vgz through resistors R1, respectively, and the output of the first amplifier 1 is connected to the input of the second amplifier 20. and is connected to the positive power supply Vcc and the negative power supply through resistors R2 to the highest potential part and the lowest potential part of the amplifier 2, respectively, and the output of the second amplifier 2 is connected to the next stage amplifier. is further connected to the nth stage, and further connected to the nth stage.
.
最高電位及び最低電位部にそれぞれＲｎ ｆ介して前記
正電源Ｖｃｃ及び負電源ＶＩＣＲＫ接続されＯＵＴ端子
よυ出力信号を得る。The positive power source Vcc and negative power source VICRK are connected to the highest potential and lowest potential portions via Rnf, respectively, to obtain an output signal from the OUT terminal.
かかる構成において小電気信号たとえば正弦波が入力端
子ＩＮより入力すると前記電気信号ｆ′ｉ第１の増幅器
ｌによって増幅されさらに、第２・・・第ｎの増幅器２
、ｎによって十分必要とする電気信号たとえば矩形波に
増＠きれる。一方第１の増幅器１の最高電位部及び最低
電位部にそれぞれ接続された抵抗器Ｒ１によって前記第
１の増幅器のダイナミックレンジは押部ｊすれ同様に出
力に近ずくＫしたがって第２、第ｎの増幅器２、ｎのダ
イナミックレンジは抑制される。この時前記抵抗Ｒ１゜
Ｒ２及びＲｎの抵抗値の関係をＲ１＞Ｒ２＞・・・〉Ｒ
ｎ≧０（地気）とした場合、前記リミッタ増幅回路は第
３図に示す様なダイナミックレンジの特性金屑する構成
となる。又この時各段の増幅器１〜ｎは差動増幅器等を
用いれば実現できる。In such a configuration, when a small electric signal, for example, a sine wave, is input from the input terminal IN, the electric signal f'i is amplified by the first amplifier l, and is further amplified by the second... nth amplifier 2.
, n can sufficiently increase the required electrical signal to, for example, a rectangular wave. On the other hand, due to the resistors R1 connected to the highest potential part and the lowest potential part of the first amplifier 1, the dynamic range of the first amplifier approaches the output K as well as the push part J. Therefore, the second and nth The dynamic range of amplifiers 2,n is suppressed. At this time, the relationship between the resistance values of the resistors R1゜R2 and Rn is R1>R2>...>R
When n≧0 (earth), the limiter amplification circuit has a configuration with dynamic range characteristics as shown in FIG. Further, at this time, each stage of amplifiers 1 to n can be realized by using a differential amplifier or the like.
本発明は以上説明した様に増幅器を数段直列に接続され
たリミッタ増幅回路において、入力信号が小さい初段の
増幅器は小さなダイナミックレンジを有し、段数金かさ
ねるごとに次第に増幅器のダイナミックレンジを広くシ
、リミッタ増幅回路のダイナミックレンジを段数に応じ
て変化を持たせるような構成によシ、リミッタ増幅回路
の電源に対する雑音の影響を最小限におさえることがで
きる効果がある。又この時前記正負の電源Ｖｃｅ及ＶＥ
ｘのいずれかが地気の場合も同様な効果がある。As explained above, in a limiter amplifier circuit in which several stages of amplifiers are connected in series, the first stage amplifier with a small input signal has a small dynamic range, and as the number of stages increases, the dynamic range of the amplifier is gradually widened. By configuring the dynamic range of the limiter amplifier circuit to vary according to the number of stages, it is possible to minimize the influence of noise on the power supply of the limiter amplifier circuit. At this time, the positive and negative power supplies Vce and VE
A similar effect occurs if any of x is earth energy.
第１図は本発明によるリミッタ増幅回路の実施例を示す
ブロック図、第２図は従来のリミッタ増幅回路を示すブ
ロック図、第３図は本発明によるリミッタ増幅回路のダ
イナミックレンジの特性を示すグラフである。
１−・・・・・増幅器１．２・・・・・・増幅器２、ｎ
・・・・−・増副器ｎＸ Ｒ１、Ｒ２，Ｒｎ・・・・・
・抵抗器。Fig. 1 is a block diagram showing an embodiment of the limiter amplifier circuit according to the present invention, Fig. 2 is a block diagram showing a conventional limiter amplifier circuit, and Fig. 3 is a graph showing the dynamic range characteristics of the limiter amplifier circuit according to the present invention. It is. 1-...Amplifier 1.2...Amplifier 2, n
...... Amplifier nX R1, R2, Rn...
·Resistor.
Claims (1)
いて、すべての段における増幅器の最高電位端及び最低
電位端は抵抗器を介して第１および第２の電源端子にそ
れぞれ接続され、各抵抗器の抵抗値は後段にいくに従っ
て小さくなっていることを特徴とするリミッタ増幅回路
。In a limiter amplifier circuit in which multiple stages of amplifiers are connected in series, the highest potential end and the lowest potential end of the amplifiers in all stages are connected to the first and second power supply terminals through resistors, respectively, and the voltage of each resistor is A limiter amplifier circuit characterized in that the resistance value decreases as it goes to the later stages.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61160062A JPS6314507A (en) | 1986-07-07 | 1986-07-07 | Limiter amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61160062A JPS6314507A (en) | 1986-07-07 | 1986-07-07 | Limiter amplifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6314507A true JPS6314507A (en) | 1988-01-21 |
Family
ID=15707076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61160062A Pending JPS6314507A (en) | 1986-07-07 | 1986-07-07 | Limiter amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6314507A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11022284B2 (en) | 2007-03-01 | 2021-06-01 | Signify Holding B.V. | Computer-controlled lighting system |
-
1986
- 1986-07-07 JP JP61160062A patent/JPS6314507A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11022284B2 (en) | 2007-03-01 | 2021-06-01 | Signify Holding B.V. | Computer-controlled lighting system |
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