JPS63301607A - Gain control amplifier circuit - Google Patents
Gain control amplifier circuitInfo
- Publication number
- JPS63301607A JPS63301607A JP13850987A JP13850987A JPS63301607A JP S63301607 A JPS63301607 A JP S63301607A JP 13850987 A JP13850987 A JP 13850987A JP 13850987 A JP13850987 A JP 13850987A JP S63301607 A JPS63301607 A JP S63301607A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- gain
- resistance
- gain control
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002131 composite material Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はトランジスタ増幅回路に関し、特に利得制御増
幅回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transistor amplifier circuit, and particularly to a gain control amplifier circuit.
従来、この種の利得制御増幅回路としては、第３図に示
す電流源トランジスタ３１とバラツキ吸収抵抗３２から
成る等価電流源３３に一方の定電圧Ｖｓｓが印加され、
この等価電流源３３に接続される１組のトランジスタ３
４．３５の入力端子３６゜３７間に入力が印加され、他
方の定電圧端子ＶＤＤに接続された負荷抵抗３８．３９
の両端の出力端子４１．４２から増幅された電圧を取り
出すことが出来る差動型増幅回路の出力端子間に挿入さ
れた可変抵抗４３の抵抗値を変化させることにより利得
制御が行なわれていた。Conventionally, in this type of gain control amplifier circuit, one constant voltage Vss is applied to an equivalent current source 33 consisting of a current source transistor 31 and a variation absorbing resistor 32 shown in FIG.
A set of transistors 3 connected to this equivalent current source 33
An input is applied between input terminals 36 and 37 of 4.35, and a load resistor 38.39 is connected to the other constant voltage terminal VDD.
Gain control was performed by changing the resistance value of a variable resistor 43 inserted between the output terminals of a differential amplifier circuit that can extract the amplified voltage from output terminals 41 and 42 at both ends of the differential amplifier circuit.
上述した従来の利得制御増幅回路は、可変抵抗４３を変
えることによシ総合の負荷抵抗値を変え利得を変化させ
ていた。即ち、負荷抵抗３８．３９の抵抗値をＲＬ、可
変抵抗４３の抵抗値を２ＲＶとすると、各トランジスタ
３４．３５の総合の負荷抵抗値ＲＴはＲＬとＲｖが並列
に接続された値几ＬＲＶ／（Ｒｒ、十Ｒｖ）となる。従
って、Ｒｖを零とすると七も零となシ、 ＲＬが無限大
の時几ＴはＲＬに等しくなる。In the conventional gain control amplifier circuit described above, by changing the variable resistor 43, the overall load resistance value is changed and the gain is changed. That is, if the resistance value of the load resistor 38.39 is RL and the resistance value of the variable resistor 43 is 2RV, the total load resistance value RT of each transistor 34.35 is the value where RL and Rv are connected in parallel. (Rr, 10Rv). Therefore, if Rv is set to zero, seven will also be zero, and when RL is infinite, T will be equal to RL.
また、この増幅回路の電圧利得はＲＴに比例するため、
可変抵抗４３を変えＲｖを変化させることによシ利得が
制御出来る。しかし、この回路の最大出力電圧は、等何
事流源の電流値Ｉｓと負荷抵抗ＲＴの積で決まるため、
利得制御を行なって利得を小さく １．た場合（ＲＴを
小さくした場合）には、同時に最大出力電圧も小さくな
り、大きな入力電力に対し歪が増加する。Also, since the voltage gain of this amplifier circuit is proportional to RT,
By changing the variable resistor 43 and changing Rv, the gain can be controlled. However, the maximum output voltage of this circuit is determined by the product of the current value Is of the current source and the load resistance RT, so
Perform gain control to reduce the gain 1. In this case (when RT is made small), the maximum output voltage also becomes small at the same time, and distortion increases with respect to large input power.
本発明の利得制御増幅回路は、等何事流源を共有するＩ
ｐｉのトランジスタとそれぞれの負荷抵抗を有する差動
型増幅回路の、これ等負荷抵抗とトランジスタとの接続
部Ａ、 Ｂ間に、固定抵抗と可変抵抗素子が直列に接
続された複合抵抗素子がそれぞれの固定抵抗の他端が異
なる接続部Ａ、 Ｂに接続される向きに接続され、こ
れら複合抵抗素子内の固定抵抗と可変抵抗素子の接続部
を２つの出力端子とを持つように構成されている。The gain control amplifier circuit of the present invention has an I
In a differential amplifier circuit having a pi transistor and each load resistor, a composite resistance element in which a fixed resistance and a variable resistance element are connected in series is connected between connection points A and B between these load resistances and the transistors. The other end of the fixed resistor is connected in a direction such that it is connected to different connection parts A and B, and the connection part between the fixed resistance and variable resistance element in these composite resistance elements is configured to have two output terminals. There is.
〔実施例〕 次に、本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す等価回路である。等何
事流源３３と１組のトランジスタ３６゜３７と１組の負
荷抵抗３８．３９を持つ差動型増幅回路の負荷抵抗３８
．３９の両端に、固定抵抗１１と可変抵抗１２が直列に
接続された１ｍの抵抗体１３．１４が、固定抵抗が各々
異なる負荷抵抗と接続されるよう逆向きに接続され、こ
れら１組の抵抗体１３．１４の固定抵抗１１と可変抵抗
１２の接続部を、それぞれ出力端子４１．４２とする増
幅回路である。FIG. 1 is an equivalent circuit showing one embodiment of the present invention. A load resistor 38 of a differential amplifier circuit having a current source 33, a set of transistors 36, 37, and a set of load resistors 38, 39
．． 39, a 1 m long resistor 13.14 in which a fixed resistor 11 and a variable resistor 12 are connected in series is connected in opposite directions so that each fixed resistor is connected to a different load resistor. This is an amplifier circuit in which the connecting portions of the fixed resistor 11 and variable resistor 12 of the body 13 and 14 are output terminals 41 and 42, respectively.
本実施例の利得制御動作は以下の様に得られる。The gain control operation of this embodiment is obtained as follows.
可変抵抗１２の抵抗値４ＲＩ２を零とした時、出力端子
４１．４２の電圧は負荷抵抗３８．３９の両端の電圧と
なシ最大の出力電圧が得られる。この時、固定抵抗１１
の抵抗値を４ＲＦ、負荷抵抗値を同じくＲＬとすると総
合の負荷抵抗値ＲＴは、それぞれトランジスタに対し、
ＲＬ ＲＦ ／ （ＲＬ＋ＲＦ ）となっている。When the resistance value 4RI2 of the variable resistor 12 is set to zero, the voltage at the output terminals 41, 42 becomes the voltage across the load resistor 38, 39, and the maximum output voltage is obtained. At this time, fixed resistance 11
If the resistance value is 4RF and the load resistance value is RL, the total load resistance value RT is, for each transistor,
RL RF/(RL+RF).
ＦＬｐをＲＬに対しある程度大きく設定した場合ＲＴは
ＲＬにほぼ等しく出来る。If FLp is set to be larger than RL to some extent, RT can be approximately equal to RL.
次に、可変抵抗１２の抵抗値４ Ｒ１２を大きくして来
ると、出力端子４１．４２の間の電圧は次第に小さくな
一す、 Ｒ，２がＲＦと等しくなった時には、出力端子
１．４２の電位は、負荷抵抗３８．３９の両端の電位の
中点にあり、両方等しくなる。従って、出力端子間の電
圧は零となシ、増幅回路の利得は零と々る。この時の総
合負荷抵抗ＲＴ ＶｉＲＬ （ＲＦ ＋ ＩＲｔＪ／
（Ｒ，Ｌ ＋ＲＰ ＋Ｒ＋ｔ ）であシ、階とＲＬ２の
値が等しいので２ＲＬＲＰ ／ （ＲＬ＋２ＲＦ）とな
る。従って、利得最小の場合の方が前述の利得最大の場
合のＲＴよシやや大きくなり、最大出力電圧を小さくす
ることなく利得を制御することが出来る。従って、利得
制御を行なって利得を下げた時に、大きな入力電圧に対
１７ても出力歪を最小限に抑えることが可能である。Next, as the resistance value 4R12 of the variable resistor 12 is increased, the voltage between the output terminals 41 and 42 gradually decreases.When R,2 becomes equal to RF, the voltage between the output terminals 1.42 and 41.42 becomes smaller. The potential is at the midpoint of the potentials at both ends of the load resistor 38 and 39, and both are equal. Therefore, the voltage between the output terminals becomes zero, and the gain of the amplifier circuit becomes zero. At this time, the total load resistance RT ViRL (RF + IRtJ/
(R,L +RP +R+t), and since the values of the floor and RL2 are equal, it becomes 2RLRP/(RL+2RF). Therefore, the RT in the case of the minimum gain is slightly larger than that in the case of the maximum gain, and the gain can be controlled without reducing the maximum output voltage. Therefore, when the gain is lowered by performing gain control, it is possible to minimize output distortion even with a large input voltage.
第２図は、本発明の他の実施例を示す等価回路で、第１
図の実施例の可変抵抗１２を、固定抵抗２１と利得制御
トランジスタ２２で置き換えた回路であり、トランジス
タ２２のオフ抵抗値（最大抵抗値）と固定抵抗２１の抵
抗値の並列接続抵抗値が、他の固定抵抗１１の値と等し
くなる様に選択することによシ、出力電力最低の条件が
得られる。トランジスタ２２の抵抗値は、コントロール
端子２３の電圧を変化させることにより、数Ωから数１
ＯＫΩ程度まで可変出来る。本実施例は固定抵抗とトラ
ンジスタのみで構成されているため、ＩＣ化に適してお
シ、また自動利得制御回路に適用することもできる。FIG. 2 is an equivalent circuit showing another embodiment of the present invention.
This is a circuit in which the variable resistor 12 in the embodiment shown in the figure is replaced with a fixed resistor 21 and a gain control transistor 22, and the parallel connection resistance value of the off resistance value (maximum resistance value) of the transistor 22 and the resistance value of the fixed resistor 21 is By selecting the value equal to the value of the other fixed resistors 11, the condition for the lowest output power can be obtained. The resistance value of the transistor 22 can be varied from several Ω to several 1 by changing the voltage at the control terminal 23.
It can be varied up to about OKΩ. Since this embodiment is composed of only fixed resistors and transistors, it is suitable for IC implementation and can also be applied to automatic gain control circuits.
以上説明したように、本発明は差動型増幅回路の負荷抵
抗部分を実施例に示す如き回路構成を取ることＫより、
利得制御増幅回路の歪を小さく抑える効果がある。As explained above, the present invention employs the circuit configuration of the load resistance portion of the differential amplifier circuit as shown in the embodiment.
This has the effect of suppressing distortion in the gain control amplifier circuit.
第１図は本発明の一実施例を示す回路図、第２図は本発
明の他の実施例を示す回路図、第３図は従来の実施例を
示す回路図である。
１１・・・・・・固定抵抗、１２・・・・・・可変抵抗
、２１・・・・・・固定抵抗、２２・・・・・・利得制
御トランジスタ、２３・・・・・・コントロール端子、
３１・・・・・・′ＢｉＲ源トランジスタ、３２・・・
・・・バラツキ吸収抵抗、３３・・・・・・等価電流源
、３４．３５・・・・・・１組のトランジスタ、３６、
３７・・・・・・入力端子、３８．３９・・・・・・負
荷抵抗、４１．４２・・・・・・出力端子、４３・・・
・・・可変抵抗。
第１図 第２記
Ｖｓｓ４Ｊ −列犯♂九FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the invention, and FIG. 3 is a circuit diagram showing a conventional embodiment. 11...Fixed resistor, 12...Variable resistor, 21...Fixed resistor, 22...Gain control transistor, 23...Control terminal ,
31...'BiR source transistor, 32...
... Variation absorbing resistance, 33... Equivalent current source, 34.35... One set of transistors, 36,
37...Input terminal, 38.39...Load resistance, 41.42...Output terminal, 43...
...Variable resistance. Figure 1. 2. Vss4J - Line criminal ♂9
Claims (1)
負荷抵抗を有する差動型増幅回路の、これ等負荷抵抗と
トランジスタとの接続部間に、固定抵抗と可変抵抗素子
が直列に接続された複合抵抗素子がそれぞれの固定抵抗
の他端が前記接続部の異なるものに接続される向きに接
続され、これら複合抵抗素子内の固定抵抗と可変抵抗素
子との接続点を出力端子としたことを特徴とする利得制
御増幅回路。A differential amplifier circuit that has a pair of transistors that share an equivalent current source and respective load resistors, and a fixed resistor and a variable resistance element are connected in series between the load resistors and the transistors. The resistive elements are connected in such a direction that the other end of each fixed resistor is connected to a different one of the connecting parts, and the connecting point between the fixed resistor and the variable resistive element in these composite resistive elements is used as an output terminal. Gain control amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13850987A JPH065808B2 (en) | 1987-06-01 | 1987-06-01 | Gain control amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13850987A JPH065808B2 (en) | 1987-06-01 | 1987-06-01 | Gain control amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63301607A true JPS63301607A (en) | 1988-12-08 |
| JPH065808B2 JPH065808B2 (en) | 1994-01-19 |
Family
ID=15223800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13850987A Expired - Lifetime JPH065808B2 (en) | 1987-06-01 | 1987-06-01 | Gain control amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065808B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002368558A (en) * | 2001-06-04 | 2002-12-20 | Asahi Kasei Microsystems Kk | Multiplier |
-
1987
- 1987-06-01 JP JP13850987A patent/JPH065808B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002368558A (en) * | 2001-06-04 | 2002-12-20 | Asahi Kasei Microsystems Kk | Multiplier |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH065808B2 (en) | 1994-01-19 |
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