JPH0630426B2 - Variable gain circuit - Google Patents
Variable gain circuitInfo
- Publication number
- JPH0630426B2 JPH0630426B2 JP20745187A JP20745187A JPH0630426B2 JP H0630426 B2 JPH0630426 B2 JP H0630426B2 JP 20745187 A JP20745187 A JP 20745187A JP 20745187 A JP20745187 A JP 20745187A JP H0630426 B2 JPH0630426 B2 JP H0630426B2
- Authority
- JP
- Japan
- Prior art keywords
- inverting input
- operational amplifier
- input terminal
- circuit
- gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明に利得可変回路に関し、特にＭＯＳ集積回路上に
構成されるＡＧＣ（自動利得制御回路）等に用いられ、
高精度、低歪の利得可変回路を実現するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a variable gain circuit, and in particular, it is used for an AGC (Automatic Gain Control Circuit) or the like formed on a MOS integrated circuit,
It realizes a high-precision, low-distortion gain variable circuit.
従来この種の利得可変回路は、第３図に示す様に、入力
端子１が非反転入力端＋に接続した演算増幅器Ａｂの出
力端と反転入力端−との間および非反転入力端−と接地
との間にそれぞれ抵抗ＲｂおよびＲｅが接続された。帰
還形増幅回路の抵抗ＲｂとＲｅのの抵抗値を可変するこ
とにより利得を可変していた。出力端子２は演算増幅器
Ａｂの出力端に接続されている。Variable gain circuit of the conventional this type, as shown in FIG. 3, the output terminal and the inverting input terminal of the operational amplifier A b to the input terminal 1 is connected to the non-inverting input terminal + - between and non-inverting input terminal - Resistors R b and R e were respectively connected between the ground and the ground. The gain has been changed by changing the resistance values of the resistors R b and R e of the feedback amplifier circuit. The output terminal 2 is connected to the output terminal of the operational amplifier A b.
第３図に示す帰還形増幅回路の利得（Ｇ）は次式の様に
なる。The gain (G) of the feedback type amplifier circuit shown in FIG. 3 is expressed by the following equation.
第３図では２つの抵抗Ｒｂ，Ｒｃの各抵抗値ｒｂ，ｒｃ
を可変する様になっているが必ずしもそうする必要はな
く、どちらか一方を可変しても良い。 In FIG. 3, the resistance values r b and r c of the two resistors R b and R c are shown.
Is variable, but it is not necessary to do so, and either one may be variable.
又、集積回路上で可変利得回路を実現しようとする場
合、半導体チップ上に可変抵抗器を実現することが困難
であるので、第４図に示す様に、演算増幅器Ａｃの出力
端と反転入力端−との間に抵抗Ｒｄを挿入するととも
に、反転入力端−と接地との間にそれぞれ抵抗値ｒe1…
ｒenの異なる抵抗Ｒe1…ＲenとスイッチＳg1…Ｓgnとの
直列回路を多数設け、スイッチＳg1…Ｓgnを選択的に投
入することにより抵抗ｒe1…ｒenを切り替えて利得を可
変する方法が用いられている。例えば、第４図におい
て、スイッチＳg1がオン状態で他のスイッチがオフであ
れば第４図の利得可変回路の利得Ｇは となる。従ってスイッチＳg1…Ｓgnを制御することによ
り、抵抗とスイッチとの直列回路をｎ個並列に設けた場
合には、（２ｎ−１）種類の利得を得ることが出来る。Also, when attempting to realize a variable gain circuit on an integrated circuit, since it is difficult to realize a variable resistor on the semiconductor chip, as shown in FIG. 4, the inverted output terminal of the operational amplifier A c A resistor Rd is inserted between the input terminal − and the resistance value r e1 ... Between the inverting input terminal − and the ground.
provided many different resistance R e1 ... series circuit of a R en and the switch S g1 ... S gn of r en, the gain by switching the resistance r e1 ... r en by selectively turned the switch S g1 ... S gn A variable method is used. For example, in FIG. 4, if the switch S g1 is on and the other switches are off, the gain G of the gain variable circuit of FIG. Becomes Therefore, by controlling the switches S g1 ... S gn , when n series circuits of resistors and switches are provided in parallel, (2 n -1) kinds of gains can be obtained.
ところが、第４図に示した従来の集積回路に形成される
利得可変回路はスイッチＳg1…Ｓgnのオン抵抗値により
利得の誤差が発生する。又、集積回路でのスイッチは機
械的なスイッチではなくトランジスタを用いたアナログ
スイッチであるので、一般的にこのアナログスイッチの
オン抵抗はアナログスイッチの両端に加わる電圧により
変動するため、利得可変回路の出力波形に歪が発生する
という欠点があった。However, in the variable gain circuit formed in the conventional integrated circuit shown in FIG. 4, a gain error occurs due to the on resistance value of the switches S g1 ... S gn . In addition, since the switch in the integrated circuit is not a mechanical switch but an analog switch using a transistor, the ON resistance of this analog switch generally fluctuates according to the voltage applied to both ends of the analog switch, so There is a drawback that the output waveform is distorted.
本発明の利得可変回路は、入力信号を増幅して出力する
演算増幅器と、この演算増幅器の出力端と反転入力端と
の間に接続された帰還抵抗と、この演算増幅器の反転入
力端と接地端との間に並列に接続された複数の帰還量設
定回路とを有し、各帰還量設定回路はそれぞれ抵抗とこ
の抵抗を選択的に接地するための演算増幅器とアナログ
スイッチとを含んで構成されるスイッチ回路との直列接
続を有している。The variable gain circuit of the present invention includes an operational amplifier that amplifies and outputs an input signal, a feedback resistor connected between the output terminal and the inverting input terminal of the operational amplifier, the inverting input terminal of the operational amplifier, and the ground. A plurality of feedback amount setting circuits connected in parallel with the ends, each feedback amount setting circuit including a resistor, an operational amplifier for selectively grounding the resistor, and an analog switch. It has a series connection with the switch circuit.
次に、本発明について図面を参照してより詳細に説明す
る。Next, the present invention will be described in more detail with reference to the drawings.
第１図は本発明の一実施例の回路図である。入力端子１
は演算増幅器Ａｆの非反転入力端＋に接続され、出力端
子２は同じく演算増幅器Ａｆの出力端に接続されてい
る。演算増幅器Ａｆの出力端と反転入力端−との間には
帰還抵抗Ｒｆが接続されている。更に演算増幅器Ａｆの
反転入力端−には帰還量設定用の抵抗Ｒ１…Ｒｎの各一
端が接続される。抵抗Ｒ１…Ｒｎの各他端はそれぞれ演
算増幅器Ａ１〜Ａｎの反転入力端−に接続されている。
各演算増幅器Ａ１〜Ａｎの反転入力端−と出力端との間
にはそれぞれアナログスイッチＳ１〜Ｓｎが接続されて
おり、非反転入力端＋は正電源Ｖ＋と接地とに切り換え
て接続する切換スイッチＳe1〜Ｓenに接続されている。FIG. 1 is a circuit diagram of an embodiment of the present invention. Input terminal 1
Is connected to the non-inverting input terminal of the operational amplifier Af +, the output terminal 2 is also connected to the output terminal of the operational amplifier A f. A feedback resistor R f is connected between the output terminal of the operational amplifier A f and the inverting input terminal −. Further, one ends of resistors R 1 ... R n for setting the feedback amount are connected to the inverting input terminal − of the operational amplifier A f . The other ends of the resistors R 1 ... R n are respectively connected to the inverting input terminals − of the operational amplifiers A 1 to A n .
Inverting input of the operational amplifier A 1 to A n - respectively are connected to the analog switches S 1 to S n, the non-inverting input terminal + is switchable between ground and a positive power supply V + between the output terminal Are connected to the changeover switches S e1 to S en .
本利得可変回路はアナログスイッチＳ１〜Ｓｎ及び切り
換えスイッチＳe1〜Ｓenにより、選択された抵抗Ｒ１〜
Ｒｎが接地されて利得の可変を行うが、ここで１つの演
算増幅器Ａｎに接続された２つのスイッチＳＮとＳ
eN（Ｎ＝１，２，３……，ｎ）は同時に動作し、一方の
スイッチＳＮがオフ状態の時他方のスイッチＳeNは正電
源Ｖ＋側に接続され、逆に一方のスイッチＳＮがオン状
態の時他方のスイッチＳeNは接地側に接続される。入力
端子１に加わる入力信号は正電源電圧と負電源電圧の範
囲内で変動するものとする。The gain variable circuit includes resistors R 1 to R 1 selected by analog switches S 1 to S n and changeover switches S e1 to S en.
R n is grounded to change the gain, but here two switches S N and S N connected to one operational amplifier A n are used.
eN (N = 1, 2, 3 ..., N) operate simultaneously, and when one switch S N is in the off state, the other switch S eN is connected to the positive power source V + side, and conversely one switch S N is connected. When N is on, the other switch S eN is connected to the ground side. The input signal applied to the input terminal 1 fluctuates within the range of the positive power supply voltage and the negative power supply voltage.
以下順を追って動作の説明を行う。The operation will be described below step by step.
まず、アナログスイッチＳ１〜Ｓｎが全てオフ状態にあ
るとすると、前述した様に切り換えスイッチＳe1〜Ｓen
は全て正電源Ｖ＋側に接続される。これは演算増幅器Ｓ
ｆがオープンループになった時に、出力が変動しない様
に電源電圧に固定するためのものである。従って必ずし
も正電源Ｖ＋にする必要もなく、負電源でもかまわな
い。又、このことは本発明を実施する上で必ずしも必要
な事ではなく、演算増幅器Ａ１〜Ａｎの非反転入力を常
に接地しておいても良い。この時抵抗Ｒ１〜Ｒｎと演算
増幅器Ａｆの反転入力端＋ｅの接続点は高インピーダン
スとなる。従って演算増幅器Ａｆで構成される増幅回路
は全帰還の状態となり、利得は“１”となる。First, assuming that all the analog switches S 1 to S n are off, the changeover switches S e1 to S en as described above.
Are all connected to the positive power supply V + side. This is the operational amplifier S
This is for fixing the power supply voltage so that the output does not fluctuate when f becomes an open loop. Therefore, it is not always necessary to use the positive power source V + , and the negative power source may be used. Moreover, this is not strictly necessary in practicing the present invention, it may be always allowed to ground the non inverting input of the operational amplifier A 1 to A n. At this time, the connection point between the resistors R 1 to R n and the inverting input terminal + e of the operational amplifier A f becomes high impedance. Therefore, the amplifier circuit composed of the operational amplifier A f is in the state of full feedback, and the gain is “1”.
次に、アナログスイッチＳ１のみオンの時について説明
する。この時、前述の様に切り換えスイッチＳe1は接地
側、切り換えスイッチＳe2〜Ｓenは正電源Ｖ＋側に接続
される。このことにより演算増幅器Ａ１のみが全帰還の
状態となる。従って、この時演算増幅器Ａ１の反転入力
端−は仮想接地となる。この場合、アナログスイッチＳ
１が某かのインピーダンスを持っていても同様の結果と
なる。Next, the case where only the analog switch S 1 is turned on will be described. At this time, as described above, the changeover switch S e1 is connected to the ground side, and the changeover switches S e2 to S en are connected to the positive power source V + side. As a result, only the operational amplifier A 1 is in the full feedback state. Therefore, at this time, the inverting input terminal − of the operational amplifier A 1 becomes virtual ground. In this case, analog switch S
The same result is obtained even if 1 has some impedance.
この時、演算増幅器Ａｆで構成される増幅回路の利得Ｇ
は抵抗ＲｆとＲ１との抵抗値ｒｆ，ｒ１できまり、 となる。At this time, the gain G of the amplifier circuit composed of the operational amplifier A f
Is the resistance values r f and r 1 of the resistances R f and R 1 , Becomes
以下同様に、アナログスイッチＳ１〜Ｓｎの組合せによ
り（２ｎ−１）種類の利得を実現することが出来る。Similarly, by combining the analog switches S 1 to S n , (2 n −1) types of gains can be realized.
第２図は本発明の他の実施例を示す回路図である。今ま
での説明では抵抗値により利得可変回路の利得を設定し
ているが、それぞれの抵抗に容量等の某かのインピーダ
ンスを並列に接続しても基本的には同様に動作する。FIG. 2 is a circuit diagram showing another embodiment of the present invention. In the above description, the gain of the variable gain circuit is set by the resistance value, but basically the same operation is achieved even if some impedance such as capacitance is connected in parallel to each resistance.
第２図に示す実施例では容量ＣａおよびＣ１〜Ｃｎを各
抵抗ＲａおよびＲa1〜Ｒanに並列に接続したものであ
る。又各演算増幅器Ａf1〜Ａfnの非反転入力端＋はそれ
ぞれ接地されている。この動作は前述の一実施例と同様
であるが、第１図の実施例が周波数特性を持たないのに
対して、本実施例は周波数特性を有する。例とて、アナ
ログスイッチＳf1のみがオン状態の時の演算幅器Ａａの
利得Ｇ（Ｓ）は となる。In the embodiment shown in FIG. 2, the capacitors C a and C 1 to C n are connected in parallel to the respective resistors R a and R a1 to R an . The non-inverting input terminals + of the operational amplifiers A f1 to A fn are grounded. This operation is similar to that of the above-described embodiment, but the embodiment of FIG. 1 does not have frequency characteristics, whereas this embodiment has frequency characteristics. As an example, the gain G (S) of the arithmetic width unit A a when only the analog switch S f1 is on is Becomes
上述の様に第２図の実施例は周波数特性を有することか
ら、可変等化器等に応用することも出来る。As described above, the embodiment shown in FIG. 2 has a frequency characteristic, so that it can be applied to a variable equalizer or the like.
以上説明したように、本発明は、演算増幅器の仮想接地
を利用して、利得可変抵抗を接地するので、アナログス
イッチのオン抵抗の影響を受けず、高精度、低歪の利得
可変回路を実現することが出来る。As described above, according to the present invention, since the variable gain resistor is grounded by using the virtual ground of the operational amplifier, the gain variable circuit with high accuracy and low distortion is realized without being affected by the on resistance of the analog switch. You can do it.
また、本発明は特に入力インピーダンスの高いＭＯＳ演
算増幅器に対して有効であるが、入力インピーダンスを
無視出来る様な抵抗値を使用すればバイポーラ演算増幅
器を用いても実現可能である。Further, the present invention is particularly effective for a MOS operational amplifier having a high input impedance, but it can also be realized by using a bipolar operational amplifier if a resistance value that can ignore the input impedance is used.
第１図は本発明の一実施例による回路図、第２図は本発
明の他の実施例による回路図、第３図及び第４図は従来
の実施例の回路図である。 １……入力端子、２……出力端子、Ａ１〜Ａｎ，Ａｆ，
Ａf1〜Ａfn，Ａａ，Ａｂ，Ａｃ……演算増幅器、Ｒ１〜
Ｒｎ，Ｒｆ，Ｒa1〜Ｒan，Ｒａ，Ｒe1〜Ｒem，Ｒｄ……
抵抗、Ｒｂ，Ｒｃ……可変抵抗、Ｓ１〜Ｓｎ，Ｓe1〜Ｓ
enＳf1〜Ｓfn，Ｓg1〜Ｓgn……スイッチ、Ｃ１〜Ｃｎ，
Ｃａ……容量。FIG. 1 is a circuit diagram according to an embodiment of the present invention, FIG. 2 is a circuit diagram according to another embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams of a conventional embodiment. 1 ... Input terminal, 2 ... Output terminal, A 1 to An , A f ,
A f1 to A fn , A a , A b , A c ... Operational amplifier, R 1 to
R n , R f , R a1 to R an , R a , R e1 to R em , R d ...
Resistance, R b, R c ...... variable resistor, S 1 ~S n, S e1 ~S
en S f1 to S fn , S g1 to S gn ... Switches, C 1 to C n ,
Ca ... Capacity.
Claims (1)
利得可変出力を得る第１の演算増幅器と、該第１の演算
増幅器の前記出力端と反転入力端との間に接続された帰
還抵抗と、前記第１の演算増幅器の前記反転入力端に共
通接続された複数の帰還量設定抵抗と、該複数の帰還量
設定抵抗のそれぞれの他端に各反転入力端が接続されか
つ非反転入力端が固定電位に接続された複数の制御用演
算増幅器と、該制御用演算増幅器のそれぞれの出力端と
反転入力端との間に接続された複数のアナログスイッチ
とを含むことを特徴とする利得可変回路。1. A first operational amplifier which receives a signal at a non-inverting input terminal and obtains a variable gain output from the output terminal, and is connected between the output terminal and the inverting input terminal of the first operational amplifier. Feedback resistors, a plurality of feedback amount setting resistors commonly connected to the inverting input terminal of the first operational amplifier, and each inverting input terminal is connected to the other end of each of the plurality of feedback amount setting resistors. A plurality of control operational amplifiers whose non-inverting input terminals are connected to a fixed potential, and a plurality of analog switches connected between respective output terminals and inverting input terminals of the control operational amplifiers. Variable gain circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20745187A JPH0630426B2 (en) | 1987-08-20 | 1987-08-20 | Variable gain circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20745187A JPH0630426B2 (en) | 1987-08-20 | 1987-08-20 | Variable gain circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6449410A JPS6449410A (en) | 1989-02-23 |
| JPH0630426B2 true JPH0630426B2 (en) | 1994-04-20 |
Family
ID=16539987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20745187A Expired - Lifetime JPH0630426B2 (en) | 1987-08-20 | 1987-08-20 | Variable gain circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0630426B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4774707B2 (en) * | 2004-09-29 | 2011-09-14 | ミツミ電機株式会社 | Amplifier circuit and input circuit |
| JP6755467B2 (en) * | 2015-05-22 | 2020-09-16 | 株式会社エヌエフ回路設計ブロック | Switching circuits and electronic circuits of electronic circuits provided with amplification means |
-
1987
- 1987-08-20 JP JP20745187A patent/JPH0630426B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6449410A (en) | 1989-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2008205560A (en) | Variable gain amplifier circuit, filter circuit and semiconductor device | |
| US5382919A (en) | Wideband constant impedance amplifiers | |
| US5760641A (en) | Controllable filter arrangement | |
| JPH0630426B2 (en) | Variable gain circuit | |
| JP3225527B2 (en) | Delay circuit | |
| JP2001144563A (en) | Variable gain amplifier system | |
| US4853609A (en) | Distortion-free, opposite-phase current source | |
| JPH04160912A (en) | Electronic variable resistor | |
| JP3951726B2 (en) | Gain control circuit and electronic volume circuit | |
| US4644193A (en) | Analog circuit for simulating a digitally controlled rheostat | |
| JPS631768B2 (en) | ||
| JPS592415A (en) | Amplifier | |
| JPS60236509A (en) | Differential variable amplifier circuit | |
| JPH02266601A (en) | Differential amplifier | |
| JP3016942B2 (en) | Gain switching circuit | |
| JP2567361B2 (en) | Pulse delay circuit | |
| JPS5846889B2 (en) | Kahenteiko Cairo | |
| JPH0614499Y2 (en) | Electronic volume buffer circuit | |
| JPH06291572A (en) | Variable gain amplifier circuit | |
| JPS5913410A (en) | Power amplifying circuit | |
| JPS6161286B2 (en) | ||
| JPS60675Y2 (en) | Signal addition circuit | |
| JPS6125312A (en) | Amplifier | |
| JP2845638B2 (en) | Variable gain circuit | |
| JPS635290Y2 (en) |